mirror of
https://github.com/SmallPond/MIT6.828_OS.git
synced 2026-04-30 13:49:48 +08:00
my solution to lab 6
This commit is contained in:
winPond
@@ -38,6 +38,12 @@ KERN_SRCFILES += kern/mpentry.S \
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kern/lapic.c \
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kern/spinlock.c
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# Source files for LAB6
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KERN_SRCFILES += kern/e100.c \
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kern/e1000.c \
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kern/pci.c \
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kern/time.c
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# Only build files if they exist.
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KERN_SRCFILES := $(wildcard $(KERN_SRCFILES))
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@@ -84,6 +90,15 @@ KERN_BINFILES += user/faultio\
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user/icode \
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fs/fs
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# Binary files for LAB6
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KERN_BINFILES += user/testtime \
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user/httpd \
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user/echosrv \
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user/echotest \
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net/testoutput \
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net/testinput \
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net/ns
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# Binary files for LAB5
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KERN_BINFILES += user/testpteshare \
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user/testfdsharing \
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150
lab/kern/e1000.c
Normal file
150
lab/kern/e1000.c
Normal file
@@ -0,0 +1,150 @@
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#include <kern/e1000.h>
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#include <kern/pmap.h>
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#include <kern/pci.h>
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#include <kern/pcireg.h>
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#include <inc/string.h>
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// LAB 6: Your driver code here
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#define E1000_LOCATE(offset) (offset >> 2)
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volatile uint32_t *e1000;
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uint32_t E1000_MAC[6] = {0x52, 0x54, 0x00, 0x12, 0x34, 0x56};
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/* 为描述符列表分配静态内存 */
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struct E1000TxDesc tx_desc_list[TX_DESC_SIZE] __attribute__((aligned (PGSIZE))) ;
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char tx_pbuf[TX_DESC_SIZE][TX_PACKET_SIZE] __attribute__((aligned (PGSIZE))) ;
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struct E1000RxDesc rx_desc_list[RX_DESC_SIZE] __attribute__((aligned (PGSIZE))) ;
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char rx_pbuf[RX_DESC_SIZE][RX_PACKET_SIZE] __attribute__((aligned (PGSIZE))) ;
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void
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e1000_transmit_init()
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{
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size_t i;
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memset(tx_desc_list, 0 , sizeof(struct E1000TxDesc) * TX_DESC_SIZE);
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for (i = 0; i < TX_DESC_SIZE; i++) {
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tx_desc_list[i].buffer_addr = PADDR(tx_pbuf[i]);
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tx_desc_list[i].status = E1000_TXD_STAT_DD;
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tx_desc_list[i].cmd = E1000_TXD_CMD_RS | E1000_TXD_CMD_EOP;
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}
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e1000[E1000_LOCATE(E1000_TDBAL)] = PADDR(tx_desc_list);
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e1000[E1000_LOCATE(E1000_TDBAH)] = 0;
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e1000[E1000_LOCATE(E1000_TDLEN)] = sizeof(struct E1000TxDesc) * TX_DESC_SIZE;
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// ensure that TDH and TDT are 0 index not offset
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e1000[E1000_LOCATE(E1000_TDH)] = 0;
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e1000[E1000_LOCATE(E1000_TDT)] = 0;
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// Initialize the Transmit Control Register (TCTL)
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e1000[E1000_LOCATE(E1000_TCTL)] = E1000_TCTL_EN |
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E1000_TCTL_PSP |
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(E1000_TCTL_CT & (0x10 << 4)) |
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(E1000_TCTL_COLD & (0x40 << 12));
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// 10 8 6
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// 10 8 12
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e1000[E1000_LOCATE(E1000_TIPG)] = 10 | (8 << 10) | (12 << 20);
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}
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int
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e1000_transmit(void *addr, size_t len)
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{
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size_t tdt = e1000[E1000_LOCATE(E1000_TDT)];
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struct E1000TxDesc *tail_desc = &tx_desc_list[tdt];
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if ( !(tail_desc->status & E1000_TXD_STAT_DD )) {
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// Status is not DD
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return -1;
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}
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memmove(tx_pbuf[tdt], addr, len);
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tail_desc->length = (uint16_t )len;
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// clear DD
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tail_desc->status &= (~E1000_TXD_STAT_DD);
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e1000[E1000_LOCATE(E1000_TDT)] = (tdt+1) % TX_DESC_SIZE;
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// cprintf("transmit a packet: %s", addr);
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return 0;
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}
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void
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e1000_set_mac_addr(uint32_t mac[])
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{
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uint32_t low = 0, high = 0;
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int i;
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for (i = 0; i < 4; i++) {
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low |= mac[i] << (8 * i);
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}
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for (i = 4; i < 6; i++) {
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high |= mac[i] << (8 * i);
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}
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e1000[E1000_LOCATE(E1000_RA)] = low;
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e1000[E1000_LOCATE(E1000_RA) + 1] = high | E1000_RAH_AV;
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}
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void
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e1000_receive_init()
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{
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size_t i;
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memset(rx_desc_list, 0 , sizeof(struct E1000RxDesc) * RX_DESC_SIZE);
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for (i = 0; i < RX_DESC_SIZE; i++) {
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rx_desc_list[i].buffer_addr = PADDR(rx_pbuf[i]);
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}
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// cprintf("mac addr %x:%x", e1000[E1000_LOCATE(E1000_RA)], e1000[E1000_LOCATE(E1000_RA) + 1] );
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e1000[E1000_LOCATE(E1000_ICS)] = 0;
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e1000[E1000_LOCATE(E1000_IMS)] = 0;
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e1000[E1000_LOCATE(E1000_RDBAL)] = PADDR(rx_desc_list);
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e1000[E1000_LOCATE(E1000_RDBAH)] = 0;
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e1000[E1000_LOCATE(E1000_RDLEN)] = sizeof(struct E1000RxDesc) * RX_DESC_SIZE;
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e1000[E1000_LOCATE(E1000_RDT)] = RX_DESC_SIZE - 1;
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// 写了两遍 RDH，查了好久的BUG。
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e1000[E1000_LOCATE(E1000_RDH)] = 0;
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e1000[E1000_LOCATE(E1000_RCTL)] = E1000_RCTL_EN | E1000_RCTL_SECRC | E1000_RCTL_BAM | E1000_RCTL_SZ_2048;
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e1000_set_mac_addr(E1000_MAC);
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}
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int e1000_receive(void *buf, size_t *len)
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{
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static size_t next = 0;
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size_t tail = e1000[E1000_LOCATE(E1000_RDT)];
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if ( !(rx_desc_list[next].status & E1000_RXD_STAT_DD) ) {
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// cprintf("no packet\n");
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return -1;
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}
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*len = rx_desc_list[next].length;
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memcpy(buf, rx_pbuf[next], *len);
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rx_desc_list[next].status &= ~E1000_RXD_STAT_DD;
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next = (next + 1) % RX_DESC_SIZE;
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e1000[E1000_LOCATE(E1000_RDT)] = (tail + 1 ) % RX_DESC_SIZE;
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cprintf("e1000_receive return 0\n");
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return 0;
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}
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int
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pci_e1000_attach(struct pci_func * pcif)
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{
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int r;
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// 使能E1000，分配 MMIO等
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pci_func_enable(pcif);
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// 映射，并保存其虚拟地址，方便访问。
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e1000 = mmio_map_region(pcif->reg_base[0], pcif->reg_size[0]);
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e1000_transmit_init();
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e1000_receive_init();
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cprintf("device status:[%08x]\n", e1000[E1000_LOCATE(E1000_DEVICE_STATUS)]);
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return 0;
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}
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135
lab/kern/e1000.h
Normal file
135
lab/kern/e1000.h
Normal file
@@ -0,0 +1,135 @@
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#ifndef JOS_KERN_E1000_H
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#define JOS_KERN_E1000_H
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#include <inc/types.h>
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#define PCI_E1000_VENDER_ID 0x8086
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#define PCI_E1000_DEVICE_ID 0x100E
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/* 循环队列的长度*/
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#define TX_DESC_SIZE 32
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#define TX_PACKET_SIZE 2048
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#define RX_DESC_SIZE 128
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#define RX_PACKET_SIZE 2048
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/* Register Set
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*
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* RW - register is both readable and writable
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*
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*/
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#define E1000_DEVICE_STATUS 0x00008 /* Device Status - RO */
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#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
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#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
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#define E1000_RCTL 0x00100 /* RX Control - RW */
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#define E1000_TCTL 0x00400 /* TX Control - RW */
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#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
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#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
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#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
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#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
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#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
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#define E1000_RA 0x05400 /* Receive Address - RW Array */
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#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
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#define E1000_TDBAH 0X03804 /* TX Descriptor Base Address High - RW */
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#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
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#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
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#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
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#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
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/* Transmit Control */
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#define E1000_TCTL_RST 0x00000001 /* Reserved */
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#define E1000_TCTL_EN 0x00000002 /* enable tx */
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#define E1000_TCTL_BCE 0x00000004 /* Reserved */
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#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
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#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
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#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
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#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
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#define E1000_TCTL_PBE 0x00800000 /* Reserved */
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#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
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#define E1000_TCTL_MULR 0x10000000 /* Reserved */
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#define E1000_RCTL_EN 0x00000002 /* enable */
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#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
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#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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/* Transmit Descriptor */
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struct E1000TxDesc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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uint16_t length; /* Data buffer length */
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uint8_t cso; /* Checksum offset */
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uint8_t cmd; /* Descriptor control */
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uint8_t status; /* Descriptor status */
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uint8_t css; /* Checksum start */
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uint16_t special;
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}__attribute__((packed));
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/* Transmit Descriptor bit definitions */
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#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
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#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
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#define E1000_TXD_CMD_EOP 0x01 /* End of Packet */
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#define E1000_TXD_CMD_RS 0x08 /* Report Status */
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#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
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#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
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#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
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#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
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/* Receive Descriptor */
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struct E1000RxDesc {
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uint64_t buffer_addr;
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uint16_t length; /* Data buffer length */
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uint16_t chksum; /* Check Sum */
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uint8_t status;
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uint8_t err;
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uint16_t special;
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};
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/* Transmit Descriptor bit definitions */
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#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
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#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
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#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
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#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
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#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
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#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
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#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
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#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
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#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
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int e1000_transmit(void *addr, size_t len);
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int e1000_receive(void *buf, size_t *len);
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#endif // SOL >= 6
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@@ -274,7 +274,8 @@ env_alloc(struct Env **newenv_store, envid_t parent_id)
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env_free_list = e->env_link;
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*newenv_store = e;
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cprintf(".%08x. new env %08x\n", curenv ? curenv->env_id : 0, e->env_id);
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// cprintf("[%08x] new env %08x\n", curenv ? curenv->env_id : 0, e->env_id);
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return 0;
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}
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@@ -416,6 +417,7 @@ env_create(uint8_t *binary, enum EnvType type)
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{
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// LAB 3: Your code here.
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struct Env *newenv;
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int ret = 0;
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if ((ret = env_alloc(&newenv, 0)) < 0) {
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@@ -426,6 +428,7 @@ env_create(uint8_t *binary, enum EnvType type)
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newenv->env_tf.tf_eflags |= FL_IOPL_MASK;
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}
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load_icode(newenv, binary);
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// If this is the file server (type == ENV_TYPE_FS) give it I/O privileges.
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// LAB 5: Your code here.
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}
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@@ -447,7 +450,8 @@ env_free(struct Env *e)
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lcr3(PADDR(kern_pgdir));
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// Note the environment's demise.
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cprintf(".%08x. free env %08x\n", curenv ? curenv->env_id : 0, e->env_id);
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// cprintf("[%08x] free env %08x\n", curenv ? curenv->env_id : 0, e->env_id);
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// Flush all mapped pages in the user portion of the address space
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static_assert(UTOP % PTSIZE == 0);
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@@ -14,6 +14,8 @@
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#include <kern/picirq.h>
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#include <kern/cpu.h>
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#include <kern/spinlock.h>
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#include <kern/time.h>
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#include <kern/pci.h>
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static void boot_aps(void);
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@@ -41,6 +43,10 @@ i386_init(void)
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// Lab 4 multitasking initialization functions
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pic_init();
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// Lab 6 hardware initialization functions
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time_init();
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pci_init();
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// Acquire the big kernel lock before waking up APs
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// Your code here:
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lock_kernel();
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@@ -50,14 +56,18 @@ i386_init(void)
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// Start fs.
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ENV_CREATE(fs_fs, ENV_TYPE_FS);
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#if !defined(TEST_NO_NS)
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// Start ns.
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ENV_CREATE(net_ns, ENV_TYPE_NS);
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#endif
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#if defined(TEST)
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// Don't touch -- used by grading script!
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ENV_CREATE(TEST, ENV_TYPE_USER);
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#else
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// Touch all you want.
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ENV_CREATE(user_icode, ENV_TYPE_USER);
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//ENV_CREATE(user_sched, ENV_TYPE_USER);
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ENV_CREATE(user_yield, ENV_TYPE_USER);
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#endif // TEST*
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// Should not be necessary - drains keyboard because interrupt has given up.
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262
lab/kern/pci.c
Normal file
262
lab/kern/pci.c
Normal file
@@ -0,0 +1,262 @@
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#include <inc/x86.h>
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#include <inc/assert.h>
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#include <inc/string.h>
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#include <kern/pci.h>
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#include <kern/pcireg.h>
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#include <kern/e1000.h>
|
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// Flag to do "lspci" at bootup
|
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static int pci_show_devs = 1;
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static int pci_show_addrs = 0;
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||||
// PCI "configuration mechanism one"
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static uint32_t pci_conf1_addr_ioport = 0x0cf8;
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static uint32_t pci_conf1_data_ioport = 0x0cfc;
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|
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// Forward declarations
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static int pci_bridge_attach(struct pci_func *pcif);
|
||||
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int pci_e1000_attach(struct pci_func * pcif);
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||||
|
||||
|
||||
// PCI driver table
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||||
struct pci_driver {
|
||||
uint32_t key1, key2;
|
||||
int (*attachfn) (struct pci_func *pcif);
|
||||
};
|
||||
|
||||
// pci_attach_class matches the class and subclass of a PCI device
|
||||
struct pci_driver pci_attach_class[] = {
|
||||
{ PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_PCI, &pci_bridge_attach },
|
||||
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
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||||
// pci_attach_vendor matches the vendor ID and device ID of a PCI device. key1
|
||||
// and key2 should be the vendor ID and device ID respectively
|
||||
struct pci_driver pci_attach_vendor[] = {
|
||||
{ PCI_E1000_VENDER_ID, PCI_E1000_DEVICE_ID, &pci_e1000_attach},
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
|
||||
static void
|
||||
pci_conf1_set_addr(uint32_t bus,
|
||||
uint32_t dev,
|
||||
uint32_t func,
|
||||
uint32_t offset)
|
||||
{
|
||||
assert(bus < 256);
|
||||
assert(dev < 32);
|
||||
assert(func < 8);
|
||||
assert(offset < 256);
|
||||
assert((offset & 0x3) == 0);
|
||||
|
||||
uint32_t v = (1 << 31) | // config-space
|
||||
(bus << 16) | (dev << 11) | (func << 8) | (offset);
|
||||
outl(pci_conf1_addr_ioport, v);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
pci_conf_read(struct pci_func *f, uint32_t off)
|
||||
{
|
||||
pci_conf1_set_addr(f->bus->busno, f->dev, f->func, off);
|
||||
return inl(pci_conf1_data_ioport);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_conf_write(struct pci_func *f, uint32_t off, uint32_t v)
|
||||
{
|
||||
pci_conf1_set_addr(f->bus->busno, f->dev, f->func, off);
|
||||
outl(pci_conf1_data_ioport, v);
|
||||
}
|
||||
|
||||
static int __attribute__((warn_unused_result))
|
||||
pci_attach_match(uint32_t key1, uint32_t key2,
|
||||
struct pci_driver *list, struct pci_func *pcif)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; list[i].attachfn; i++) {
|
||||
if (list[i].key1 == key1 && list[i].key2 == key2) {
|
||||
int r = list[i].attachfn(pcif);
|
||||
if (r > 0)
|
||||
return r;
|
||||
if (r < 0)
|
||||
cprintf("pci_attach_match: attaching "
|
||||
"%x.%x (%p): e\n",
|
||||
key1, key2, list[i].attachfn, r);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
pci_attach(struct pci_func *f)
|
||||
{
|
||||
return
|
||||
pci_attach_match(PCI_CLASS(f->dev_class),
|
||||
PCI_SUBCLASS(f->dev_class),
|
||||
&pci_attach_class[0], f) ||
|
||||
pci_attach_match(PCI_VENDOR(f->dev_id),
|
||||
PCI_PRODUCT(f->dev_id),
|
||||
&pci_attach_vendor[0], f);
|
||||
}
|
||||
|
||||
static const char *pci_class[] =
|
||||
{
|
||||
[0x0] = "Unknown",
|
||||
[0x1] = "Storage controller",
|
||||
[0x2] = "Network controller",
|
||||
[0x3] = "Display controller",
|
||||
[0x4] = "Multimedia device",
|
||||
[0x5] = "Memory controller",
|
||||
[0x6] = "Bridge device",
|
||||
};
|
||||
|
||||
static void
|
||||
pci_print_func(struct pci_func *f)
|
||||
{
|
||||
const char *class = pci_class[0];
|
||||
if (PCI_CLASS(f->dev_class) < ARRAY_SIZE(pci_class))
|
||||
class = pci_class[PCI_CLASS(f->dev_class)];
|
||||
|
||||
cprintf("PCI: %02x:%02x.%d: %04x:%04x: class: %x.%x (%s) irq: %d\n",
|
||||
f->bus->busno, f->dev, f->func,
|
||||
PCI_VENDOR(f->dev_id), PCI_PRODUCT(f->dev_id),
|
||||
PCI_CLASS(f->dev_class), PCI_SUBCLASS(f->dev_class), class,
|
||||
f->irq_line);
|
||||
}
|
||||
|
||||
static int
|
||||
pci_scan_bus(struct pci_bus *bus)
|
||||
{
|
||||
int totaldev = 0;
|
||||
struct pci_func df;
|
||||
memset(&df, 0, sizeof(df));
|
||||
df.bus = bus;
|
||||
|
||||
for (df.dev = 0; df.dev < 32; df.dev++) {
|
||||
uint32_t bhlc = pci_conf_read(&df, PCI_BHLC_REG);
|
||||
if (PCI_HDRTYPE_TYPE(bhlc) > 1) // Unsupported or no device
|
||||
continue;
|
||||
|
||||
totaldev++;
|
||||
|
||||
struct pci_func f = df;
|
||||
for (f.func = 0; f.func < (PCI_HDRTYPE_MULTIFN(bhlc) ? 8 : 1);
|
||||
f.func++) {
|
||||
struct pci_func af = f;
|
||||
|
||||
af.dev_id = pci_conf_read(&f, PCI_ID_REG);
|
||||
if (PCI_VENDOR(af.dev_id) == 0xffff)
|
||||
continue;
|
||||
|
||||
uint32_t intr = pci_conf_read(&af, PCI_INTERRUPT_REG);
|
||||
af.irq_line = PCI_INTERRUPT_LINE(intr);
|
||||
|
||||
af.dev_class = pci_conf_read(&af, PCI_CLASS_REG);
|
||||
if (pci_show_devs)
|
||||
pci_print_func(&af);
|
||||
pci_attach(&af);
|
||||
}
|
||||
}
|
||||
|
||||
return totaldev;
|
||||
}
|
||||
|
||||
static int
|
||||
pci_bridge_attach(struct pci_func *pcif)
|
||||
{
|
||||
uint32_t ioreg = pci_conf_read(pcif, PCI_BRIDGE_STATIO_REG);
|
||||
uint32_t busreg = pci_conf_read(pcif, PCI_BRIDGE_BUS_REG);
|
||||
|
||||
if (PCI_BRIDGE_IO_32BITS(ioreg)) {
|
||||
cprintf("PCI: %02x:%02x.%d: 32-bit bridge IO not supported.\n",
|
||||
pcif->bus->busno, pcif->dev, pcif->func);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pci_bus nbus;
|
||||
memset(&nbus, 0, sizeof(nbus));
|
||||
nbus.parent_bridge = pcif;
|
||||
nbus.busno = (busreg >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & 0xff;
|
||||
|
||||
if (pci_show_devs)
|
||||
cprintf("PCI: %02x:%02x.%d: bridge to PCI bus %d--%d\n",
|
||||
pcif->bus->busno, pcif->dev, pcif->func,
|
||||
nbus.busno,
|
||||
(busreg >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) & 0xff);
|
||||
|
||||
pci_scan_bus(&nbus);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// External PCI subsystem interface
|
||||
|
||||
void
|
||||
pci_func_enable(struct pci_func *f)
|
||||
{
|
||||
pci_conf_write(f, PCI_COMMAND_STATUS_REG,
|
||||
PCI_COMMAND_IO_ENABLE |
|
||||
PCI_COMMAND_MEM_ENABLE |
|
||||
PCI_COMMAND_MASTER_ENABLE);
|
||||
|
||||
uint32_t bar_width;
|
||||
uint32_t bar;
|
||||
for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END;
|
||||
bar += bar_width)
|
||||
{
|
||||
uint32_t oldv = pci_conf_read(f, bar);
|
||||
|
||||
bar_width = 4;
|
||||
pci_conf_write(f, bar, 0xffffffff);
|
||||
uint32_t rv = pci_conf_read(f, bar);
|
||||
|
||||
if (rv == 0)
|
||||
continue;
|
||||
|
||||
int regnum = PCI_MAPREG_NUM(bar);
|
||||
uint32_t base, size;
|
||||
if (PCI_MAPREG_TYPE(rv) == PCI_MAPREG_TYPE_MEM) {
|
||||
if (PCI_MAPREG_MEM_TYPE(rv) == PCI_MAPREG_MEM_TYPE_64BIT)
|
||||
bar_width = 8;
|
||||
|
||||
size = PCI_MAPREG_MEM_SIZE(rv);
|
||||
base = PCI_MAPREG_MEM_ADDR(oldv);
|
||||
if (pci_show_addrs)
|
||||
cprintf(" mem region %d: %d bytes at 0x%x\n",
|
||||
regnum, size, base);
|
||||
} else {
|
||||
size = PCI_MAPREG_IO_SIZE(rv);
|
||||
base = PCI_MAPREG_IO_ADDR(oldv);
|
||||
if (pci_show_addrs)
|
||||
cprintf(" io region %d: %d bytes at 0x%x\n",
|
||||
regnum, size, base);
|
||||
}
|
||||
|
||||
pci_conf_write(f, bar, oldv);
|
||||
f->reg_base[regnum] = base;
|
||||
f->reg_size[regnum] = size;
|
||||
|
||||
if (size && !base)
|
||||
cprintf("PCI device %02x:%02x.%d (%04x:%04x) "
|
||||
"may be misconfigured: "
|
||||
"region %d: base 0x%x, size %d\n",
|
||||
f->bus->busno, f->dev, f->func,
|
||||
PCI_VENDOR(f->dev_id), PCI_PRODUCT(f->dev_id),
|
||||
regnum, base, size);
|
||||
}
|
||||
|
||||
cprintf("PCI function %02x:%02x.%d (%04x:%04x) enabled\n",
|
||||
f->bus->busno, f->dev, f->func,
|
||||
PCI_VENDOR(f->dev_id), PCI_PRODUCT(f->dev_id));
|
||||
}
|
||||
|
||||
int
|
||||
pci_init(void)
|
||||
{
|
||||
static struct pci_bus root_bus;
|
||||
memset(&root_bus, 0, sizeof(root_bus));
|
||||
|
||||
return pci_scan_bus(&root_bus);
|
||||
}
|
||||
33
lab/kern/pci.h
Normal file
33
lab/kern/pci.h
Normal file
@@ -0,0 +1,33 @@
|
||||
#ifndef JOS_KERN_PCI_H
|
||||
#define JOS_KERN_PCI_H
|
||||
|
||||
#include <inc/types.h>
|
||||
|
||||
// PCI subsystem interface
|
||||
enum { pci_res_bus, pci_res_mem, pci_res_io, pci_res_max };
|
||||
|
||||
struct pci_bus;
|
||||
|
||||
struct pci_func {
|
||||
struct pci_bus *bus; // Primary bus for bridges
|
||||
|
||||
uint32_t dev;
|
||||
uint32_t func;
|
||||
|
||||
uint32_t dev_id;
|
||||
uint32_t dev_class;
|
||||
|
||||
uint32_t reg_base[6];
|
||||
uint32_t reg_size[6];
|
||||
uint8_t irq_line;
|
||||
};
|
||||
|
||||
struct pci_bus {
|
||||
struct pci_func *parent_bridge;
|
||||
uint32_t busno;
|
||||
};
|
||||
|
||||
int pci_init(void);
|
||||
void pci_func_enable(struct pci_func *f);
|
||||
|
||||
#endif
|
||||
710
lab/kern/pcireg.h
Normal file
710
lab/kern/pcireg.h
Normal file
@@ -0,0 +1,710 @@
|
||||
/* $NetBSD: pcireg.h,v 1.45 2004/02/04 06:58:24 soren Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, 1996, 1999, 2000
|
||||
* Christopher G. Demetriou. All rights reserved.
|
||||
* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Charles M. Hannum.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_PCI_PCIREG_H_
|
||||
#define _DEV_PCI_PCIREG_H_
|
||||
|
||||
/*
|
||||
* Standardized PCI configuration information
|
||||
*
|
||||
* XXX This is not complete.
|
||||
*/
|
||||
|
||||
#include <inc/types.h>
|
||||
|
||||
/*
|
||||
* Device identification register; contains a vendor ID and a device ID.
|
||||
*/
|
||||
#define PCI_ID_REG 0x00
|
||||
|
||||
typedef uint16_t pci_vendor_id_t;
|
||||
typedef uint16_t pci_product_id_t;
|
||||
|
||||
#define PCI_VENDOR_SHIFT 0
|
||||
#define PCI_VENDOR_MASK 0xffff
|
||||
#define PCI_VENDOR(id) \
|
||||
(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
|
||||
|
||||
#define PCI_PRODUCT_SHIFT 16
|
||||
#define PCI_PRODUCT_MASK 0xffff
|
||||
#define PCI_PRODUCT(id) \
|
||||
(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
|
||||
|
||||
#define PCI_ID_CODE(vid,pid) \
|
||||
((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
|
||||
(((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \
|
||||
|
||||
/*
|
||||
* Command and status register.
|
||||
*/
|
||||
#define PCI_COMMAND_STATUS_REG 0x04
|
||||
#define PCI_COMMAND_SHIFT 0
|
||||
#define PCI_COMMAND_MASK 0xffff
|
||||
#define PCI_STATUS_SHIFT 16
|
||||
#define PCI_STATUS_MASK 0xffff
|
||||
|
||||
#define PCI_COMMAND_STATUS_CODE(cmd,stat) \
|
||||
((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \
|
||||
(((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \
|
||||
|
||||
#define PCI_COMMAND_IO_ENABLE 0x00000001
|
||||
#define PCI_COMMAND_MEM_ENABLE 0x00000002
|
||||
#define PCI_COMMAND_MASTER_ENABLE 0x00000004
|
||||
#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
|
||||
#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
|
||||
#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
|
||||
#define PCI_COMMAND_PARITY_ENABLE 0x00000040
|
||||
#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
|
||||
#define PCI_COMMAND_SERR_ENABLE 0x00000100
|
||||
#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
|
||||
|
||||
#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
|
||||
#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
|
||||
#define PCI_STATUS_UDF_SUPPORT 0x00400000
|
||||
#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
|
||||
#define PCI_STATUS_PARITY_ERROR 0x01000000
|
||||
#define PCI_STATUS_DEVSEL_FAST 0x00000000
|
||||
#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
|
||||
#define PCI_STATUS_DEVSEL_SLOW 0x04000000
|
||||
#define PCI_STATUS_DEVSEL_MASK 0x06000000
|
||||
#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
|
||||
#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
|
||||
#define PCI_STATUS_MASTER_ABORT 0x20000000
|
||||
#define PCI_STATUS_SPECIAL_ERROR 0x40000000
|
||||
#define PCI_STATUS_PARITY_DETECT 0x80000000
|
||||
|
||||
/*
|
||||
* PCI Class and Revision Register; defines type and revision of device.
|
||||
*/
|
||||
#define PCI_CLASS_REG 0x08
|
||||
|
||||
typedef uint8_t pci_class_t;
|
||||
typedef uint8_t pci_subclass_t;
|
||||
typedef uint8_t pci_interface_t;
|
||||
typedef uint8_t pci_revision_t;
|
||||
|
||||
#define PCI_CLASS_SHIFT 24
|
||||
#define PCI_CLASS_MASK 0xff
|
||||
#define PCI_CLASS(cr) \
|
||||
(((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
|
||||
|
||||
#define PCI_SUBCLASS_SHIFT 16
|
||||
#define PCI_SUBCLASS_MASK 0xff
|
||||
#define PCI_SUBCLASS(cr) \
|
||||
(((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
|
||||
|
||||
#define PCI_INTERFACE_SHIFT 8
|
||||
#define PCI_INTERFACE_MASK 0xff
|
||||
#define PCI_INTERFACE(cr) \
|
||||
(((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
|
||||
|
||||
#define PCI_REVISION_SHIFT 0
|
||||
#define PCI_REVISION_MASK 0xff
|
||||
#define PCI_REVISION(cr) \
|
||||
(((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
|
||||
|
||||
#define PCI_CLASS_CODE(mainclass, subclass, interface) \
|
||||
((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
|
||||
(((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
|
||||
(((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
|
||||
|
||||
/* base classes */
|
||||
#define PCI_CLASS_PREHISTORIC 0x00
|
||||
#define PCI_CLASS_MASS_STORAGE 0x01
|
||||
#define PCI_CLASS_NETWORK 0x02
|
||||
#define PCI_CLASS_DISPLAY 0x03
|
||||
#define PCI_CLASS_MULTIMEDIA 0x04
|
||||
#define PCI_CLASS_MEMORY 0x05
|
||||
#define PCI_CLASS_BRIDGE 0x06
|
||||
#define PCI_CLASS_COMMUNICATIONS 0x07
|
||||
#define PCI_CLASS_SYSTEM 0x08
|
||||
#define PCI_CLASS_INPUT 0x09
|
||||
#define PCI_CLASS_DOCK 0x0a
|
||||
#define PCI_CLASS_PROCESSOR 0x0b
|
||||
#define PCI_CLASS_SERIALBUS 0x0c
|
||||
#define PCI_CLASS_WIRELESS 0x0d
|
||||
#define PCI_CLASS_I2O 0x0e
|
||||
#define PCI_CLASS_SATCOM 0x0f
|
||||
#define PCI_CLASS_CRYPTO 0x10
|
||||
#define PCI_CLASS_DASP 0x11
|
||||
#define PCI_CLASS_UNDEFINED 0xff
|
||||
|
||||
/* 0x00 prehistoric subclasses */
|
||||
#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
|
||||
#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
|
||||
|
||||
/* 0x01 mass storage subclasses */
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
|
||||
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
|
||||
|
||||
/* 0x02 network subclasses */
|
||||
#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
|
||||
#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
|
||||
#define PCI_SUBCLASS_NETWORK_FDDI 0x02
|
||||
#define PCI_SUBCLASS_NETWORK_ATM 0x03
|
||||
#define PCI_SUBCLASS_NETWORK_ISDN 0x04
|
||||
#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
|
||||
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
|
||||
#define PCI_SUBCLASS_NETWORK_MISC 0x80
|
||||
|
||||
/* 0x03 display subclasses */
|
||||
#define PCI_SUBCLASS_DISPLAY_VGA 0x00
|
||||
#define PCI_SUBCLASS_DISPLAY_XGA 0x01
|
||||
#define PCI_SUBCLASS_DISPLAY_3D 0x02
|
||||
#define PCI_SUBCLASS_DISPLAY_MISC 0x80
|
||||
|
||||
/* 0x04 multimedia subclasses */
|
||||
#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
|
||||
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
|
||||
#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
|
||||
#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
|
||||
|
||||
/* 0x05 memory subclasses */
|
||||
#define PCI_SUBCLASS_MEMORY_RAM 0x00
|
||||
#define PCI_SUBCLASS_MEMORY_FLASH 0x01
|
||||
#define PCI_SUBCLASS_MEMORY_MISC 0x80
|
||||
|
||||
/* 0x06 bridge subclasses */
|
||||
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
|
||||
#define PCI_SUBCLASS_BRIDGE_ISA 0x01
|
||||
#define PCI_SUBCLASS_BRIDGE_EISA 0x02
|
||||
#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */
|
||||
#define PCI_SUBCLASS_BRIDGE_PCI 0x04
|
||||
#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
|
||||
#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
|
||||
#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
|
||||
#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
|
||||
#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
|
||||
#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
|
||||
#define PCI_SUBCLASS_BRIDGE_MISC 0x80
|
||||
|
||||
/* 0x07 communications subclasses */
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
|
||||
#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
|
||||
|
||||
/* 0x08 system subclasses */
|
||||
#define PCI_SUBCLASS_SYSTEM_PIC 0x00
|
||||
#define PCI_SUBCLASS_SYSTEM_DMA 0x01
|
||||
#define PCI_SUBCLASS_SYSTEM_TIMER 0x02
|
||||
#define PCI_SUBCLASS_SYSTEM_RTC 0x03
|
||||
#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
|
||||
#define PCI_SUBCLASS_SYSTEM_MISC 0x80
|
||||
|
||||
/* 0x09 input subclasses */
|
||||
#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
|
||||
#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
|
||||
#define PCI_SUBCLASS_INPUT_MOUSE 0x02
|
||||
#define PCI_SUBCLASS_INPUT_SCANNER 0x03
|
||||
#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
|
||||
#define PCI_SUBCLASS_INPUT_MISC 0x80
|
||||
|
||||
/* 0x0a dock subclasses */
|
||||
#define PCI_SUBCLASS_DOCK_GENERIC 0x00
|
||||
#define PCI_SUBCLASS_DOCK_MISC 0x80
|
||||
|
||||
/* 0x0b processor subclasses */
|
||||
#define PCI_SUBCLASS_PROCESSOR_386 0x00
|
||||
#define PCI_SUBCLASS_PROCESSOR_486 0x01
|
||||
#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
|
||||
#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
|
||||
#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
|
||||
#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
|
||||
#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
|
||||
|
||||
/* 0x0c serial bus subclasses */
|
||||
#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
|
||||
#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
|
||||
#define PCI_SUBCLASS_SERIALBUS_SSA 0x02
|
||||
#define PCI_SUBCLASS_SERIALBUS_USB 0x03
|
||||
#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
|
||||
#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
|
||||
#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
|
||||
#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
|
||||
#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
|
||||
#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
|
||||
|
||||
/* 0x0d wireless subclasses */
|
||||
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
|
||||
#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
|
||||
#define PCI_SUBCLASS_WIRELESS_RF 0x10
|
||||
#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
|
||||
#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
|
||||
#define PCI_SUBCLASS_WIRELESS_802_11A 0x20
|
||||
#define PCI_SUBCLASS_WIRELESS_802_11B 0x21
|
||||
#define PCI_SUBCLASS_WIRELESS_MISC 0x80
|
||||
|
||||
/* 0x0e I2O (Intelligent I/O) subclasses */
|
||||
#define PCI_SUBCLASS_I2O_STANDARD 0x00
|
||||
|
||||
/* 0x0f satellite communication subclasses */
|
||||
/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
|
||||
#define PCI_SUBCLASS_SATCOM_TV 0x01
|
||||
#define PCI_SUBCLASS_SATCOM_AUDIO 0x02
|
||||
#define PCI_SUBCLASS_SATCOM_VOICE 0x03
|
||||
#define PCI_SUBCLASS_SATCOM_DATA 0x04
|
||||
|
||||
/* 0x10 encryption/decryption subclasses */
|
||||
#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
|
||||
#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
|
||||
#define PCI_SUBCLASS_CRYPTO_MISC 0x80
|
||||
|
||||
/* 0x11 data acquisition and signal processing subclasses */
|
||||
#define PCI_SUBCLASS_DASP_DPIO 0x00
|
||||
#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
|
||||
#define PCI_SUBCLASS_DASP_SYNC 0x10
|
||||
#define PCI_SUBCLASS_DASP_MGMT 0x20
|
||||
#define PCI_SUBCLASS_DASP_MISC 0x80
|
||||
|
||||
/*
|
||||
* PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
|
||||
*/
|
||||
#define PCI_BHLC_REG 0x0c
|
||||
|
||||
#define PCI_BIST_SHIFT 24
|
||||
#define PCI_BIST_MASK 0xff
|
||||
#define PCI_BIST(bhlcr) \
|
||||
(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
|
||||
|
||||
#define PCI_HDRTYPE_SHIFT 16
|
||||
#define PCI_HDRTYPE_MASK 0xff
|
||||
#define PCI_HDRTYPE(bhlcr) \
|
||||
(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
|
||||
|
||||
#define PCI_HDRTYPE_TYPE(bhlcr) \
|
||||
(PCI_HDRTYPE(bhlcr) & 0x7f)
|
||||
#define PCI_HDRTYPE_MULTIFN(bhlcr) \
|
||||
((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
|
||||
|
||||
#define PCI_LATTIMER_SHIFT 8
|
||||
#define PCI_LATTIMER_MASK 0xff
|
||||
#define PCI_LATTIMER(bhlcr) \
|
||||
(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
|
||||
|
||||
#define PCI_CACHELINE_SHIFT 0
|
||||
#define PCI_CACHELINE_MASK 0xff
|
||||
#define PCI_CACHELINE(bhlcr) \
|
||||
(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
|
||||
|
||||
#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \
|
||||
((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \
|
||||
(((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \
|
||||
(((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \
|
||||
(((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \
|
||||
(((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
|
||||
|
||||
/*
|
||||
* PCI header type
|
||||
*/
|
||||
#define PCI_HDRTYPE_DEVICE 0
|
||||
#define PCI_HDRTYPE_PPB 1
|
||||
#define PCI_HDRTYPE_PCB 2
|
||||
|
||||
/*
|
||||
* Mapping registers
|
||||
*/
|
||||
#define PCI_MAPREG_START 0x10
|
||||
#define PCI_MAPREG_END 0x28
|
||||
#define PCI_MAPREG_ROM 0x30
|
||||
#define PCI_MAPREG_PPB_END 0x18
|
||||
#define PCI_MAPREG_PCB_END 0x14
|
||||
|
||||
#define PCI_MAPREG_TYPE(mr) \
|
||||
((mr) & PCI_MAPREG_TYPE_MASK)
|
||||
#define PCI_MAPREG_TYPE_MASK 0x00000001
|
||||
|
||||
#define PCI_MAPREG_TYPE_MEM 0x00000000
|
||||
#define PCI_MAPREG_TYPE_IO 0x00000001
|
||||
#define PCI_MAPREG_ROM_ENABLE 0x00000001
|
||||
|
||||
#define PCI_MAPREG_MEM_TYPE(mr) \
|
||||
((mr) & PCI_MAPREG_MEM_TYPE_MASK)
|
||||
#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
|
||||
|
||||
#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
|
||||
#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
|
||||
#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
|
||||
|
||||
#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
|
||||
(((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
|
||||
#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
|
||||
|
||||
#define PCI_MAPREG_MEM_ADDR(mr) \
|
||||
((mr) & PCI_MAPREG_MEM_ADDR_MASK)
|
||||
#define PCI_MAPREG_MEM_SIZE(mr) \
|
||||
(PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
|
||||
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
|
||||
|
||||
#define PCI_MAPREG_MEM64_ADDR(mr) \
|
||||
((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
|
||||
#define PCI_MAPREG_MEM64_SIZE(mr) \
|
||||
(PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
|
||||
#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
|
||||
|
||||
#define PCI_MAPREG_IO_ADDR(mr) \
|
||||
((mr) & PCI_MAPREG_IO_ADDR_MASK)
|
||||
#define PCI_MAPREG_IO_SIZE(mr) \
|
||||
(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
|
||||
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
|
||||
|
||||
#define PCI_MAPREG_SIZE_TO_MASK(size) \
|
||||
(-(size))
|
||||
|
||||
#define PCI_MAPREG_NUM(offset) \
|
||||
(((unsigned)(offset)-PCI_MAPREG_START)/4)
|
||||
|
||||
|
||||
/*
|
||||
* Cardbus CIS pointer (PCI rev. 2.1)
|
||||
*/
|
||||
#define PCI_CARDBUS_CIS_REG 0x28
|
||||
|
||||
/*
|
||||
* Subsystem identification register; contains a vendor ID and a device ID.
|
||||
* Types/macros for PCI_ID_REG apply.
|
||||
* (PCI rev. 2.1)
|
||||
*/
|
||||
#define PCI_SUBSYS_ID_REG 0x2c
|
||||
|
||||
/*
|
||||
* Capabilities link list (PCI rev. 2.2)
|
||||
*/
|
||||
#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
|
||||
#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
|
||||
#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
|
||||
#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
|
||||
#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
|
||||
|
||||
#define PCI_CAP_RESERVED0 0x00
|
||||
#define PCI_CAP_PWRMGMT 0x01
|
||||
#define PCI_CAP_AGP 0x02
|
||||
#define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf)
|
||||
#define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf)
|
||||
#define PCI_CAP_VPD 0x03
|
||||
#define PCI_CAP_SLOTID 0x04
|
||||
#define PCI_CAP_MSI 0x05
|
||||
#define PCI_CAP_CPCI_HOTSWAP 0x06
|
||||
#define PCI_CAP_PCIX 0x07
|
||||
#define PCI_CAP_LDT 0x08
|
||||
#define PCI_CAP_VENDSPEC 0x09
|
||||
#define PCI_CAP_DEBUGPORT 0x0a
|
||||
#define PCI_CAP_CPCI_RSRCCTL 0x0b
|
||||
#define PCI_CAP_HOTPLUG 0x0c
|
||||
#define PCI_CAP_AGP8 0x0e
|
||||
#define PCI_CAP_SECURE 0x0f
|
||||
#define PCI_CAP_PCIEXPRESS 0x10
|
||||
#define PCI_CAP_MSIX 0x11
|
||||
|
||||
/*
|
||||
* Vital Product Data; access via capability pointer (PCI rev 2.2).
|
||||
*/
|
||||
#define PCI_VPD_ADDRESS_MASK 0x7fff
|
||||
#define PCI_VPD_ADDRESS_SHIFT 16
|
||||
#define PCI_VPD_ADDRESS(ofs) \
|
||||
(((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
|
||||
#define PCI_VPD_DATAREG(ofs) ((ofs) + 4)
|
||||
#define PCI_VPD_OPFLAG 0x80000000
|
||||
|
||||
/*
|
||||
* Power Management Capability; access via capability pointer.
|
||||
*/
|
||||
|
||||
/* Power Management Capability Register */
|
||||
#define PCI_PMCR 0x02
|
||||
#define PCI_PMCR_D1SUPP 0x0200
|
||||
#define PCI_PMCR_D2SUPP 0x0400
|
||||
/* Power Management Control Status Register */
|
||||
#define PCI_PMCSR 0x04
|
||||
#define PCI_PMCSR_STATE_MASK 0x03
|
||||
#define PCI_PMCSR_STATE_D0 0x00
|
||||
#define PCI_PMCSR_STATE_D1 0x01
|
||||
#define PCI_PMCSR_STATE_D2 0x02
|
||||
#define PCI_PMCSR_STATE_D3 0x03
|
||||
|
||||
/*
|
||||
* PCI-X capability.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit
|
||||
* word at the capability; the lower 16 bits are the capability ID and
|
||||
* next capability pointer).
|
||||
*
|
||||
* Since we always read PCI config space in 32-bit words, we define these
|
||||
* as 32-bit values, offset and shifted appropriately. Make sure you perform
|
||||
* the appropriate R/M/W cycles!
|
||||
*/
|
||||
#define PCI_PCIX_CMD 0x00
|
||||
#define PCI_PCIX_CMD_PERR_RECOVER 0x00010000
|
||||
#define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000
|
||||
#define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000
|
||||
#define PCI_PCIX_CMD_BYTECNT_SHIFT 18
|
||||
#define PCI_PCIX_CMD_BCNT_512 0x00000000
|
||||
#define PCI_PCIX_CMD_BCNT_1024 0x00040000
|
||||
#define PCI_PCIX_CMD_BCNT_2048 0x00080000
|
||||
#define PCI_PCIX_CMD_BCNT_4096 0x000c0000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_1 0x00000000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_2 0x00100000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_3 0x00200000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_4 0x00300000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_8 0x00400000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_12 0x00500000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_16 0x00600000
|
||||
#define PCI_PCIX_CMD_SPLTRANS_32 0x00700000
|
||||
|
||||
/*
|
||||
* Status. 32 bits at offset 4.
|
||||
*/
|
||||
#define PCI_PCIX_STATUS 0x04
|
||||
#define PCI_PCIX_STATUS_FN_MASK 0x00000007
|
||||
#define PCI_PCIX_STATUS_DEV_MASK 0x000000f8
|
||||
#define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00
|
||||
#define PCI_PCIX_STATUS_64BIT 0x00010000
|
||||
#define PCI_PCIX_STATUS_133 0x00020000
|
||||
#define PCI_PCIX_STATUS_SPLDISC 0x00040000
|
||||
#define PCI_PCIX_STATUS_SPLUNEX 0x00080000
|
||||
#define PCI_PCIX_STATUS_DEVCPLX 0x00100000
|
||||
#define PCI_PCIX_STATUS_MAXB_MASK 0x00600000
|
||||
#define PCI_PCIX_STATUS_MAXB_SHIFT 21
|
||||
#define PCI_PCIX_STATUS_MAXB_512 0x00000000
|
||||
#define PCI_PCIX_STATUS_MAXB_1024 0x00200000
|
||||
#define PCI_PCIX_STATUS_MAXB_2048 0x00400000
|
||||
#define PCI_PCIX_STATUS_MAXB_4096 0x00600000
|
||||
#define PCI_PCIX_STATUS_MAXST_MASK 0x03800000
|
||||
#define PCI_PCIX_STATUS_MAXST_1 0x00000000
|
||||
#define PCI_PCIX_STATUS_MAXST_2 0x00800000
|
||||
#define PCI_PCIX_STATUS_MAXST_3 0x01000000
|
||||
#define PCI_PCIX_STATUS_MAXST_4 0x01800000
|
||||
#define PCI_PCIX_STATUS_MAXST_8 0x02000000
|
||||
#define PCI_PCIX_STATUS_MAXST_12 0x02800000
|
||||
#define PCI_PCIX_STATUS_MAXST_16 0x03000000
|
||||
#define PCI_PCIX_STATUS_MAXST_32 0x03800000
|
||||
#define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_1K 0x00000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_2K 0x04000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_4K 0x08000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_16K 0x10000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_32K 0x14000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_64K 0x18000000
|
||||
#define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000
|
||||
#define PCI_PCIX_STATUS_SCERR 0x20000000
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Configuration Register; contains interrupt pin and line.
|
||||
*/
|
||||
#define PCI_INTERRUPT_REG 0x3c
|
||||
|
||||
typedef uint8_t pci_intr_latency_t;
|
||||
typedef uint8_t pci_intr_grant_t;
|
||||
typedef uint8_t pci_intr_pin_t;
|
||||
typedef uint8_t pci_intr_line_t;
|
||||
|
||||
#define PCI_MAX_LAT_SHIFT 24
|
||||
#define PCI_MAX_LAT_MASK 0xff
|
||||
#define PCI_MAX_LAT(icr) \
|
||||
(((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
|
||||
|
||||
#define PCI_MIN_GNT_SHIFT 16
|
||||
#define PCI_MIN_GNT_MASK 0xff
|
||||
#define PCI_MIN_GNT(icr) \
|
||||
(((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
|
||||
|
||||
#define PCI_INTERRUPT_GRANT_SHIFT 24
|
||||
#define PCI_INTERRUPT_GRANT_MASK 0xff
|
||||
#define PCI_INTERRUPT_GRANT(icr) \
|
||||
(((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
|
||||
|
||||
#define PCI_INTERRUPT_LATENCY_SHIFT 16
|
||||
#define PCI_INTERRUPT_LATENCY_MASK 0xff
|
||||
#define PCI_INTERRUPT_LATENCY(icr) \
|
||||
(((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
|
||||
|
||||
#define PCI_INTERRUPT_PIN_SHIFT 8
|
||||
#define PCI_INTERRUPT_PIN_MASK 0xff
|
||||
#define PCI_INTERRUPT_PIN(icr) \
|
||||
(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
|
||||
|
||||
#define PCI_INTERRUPT_LINE_SHIFT 0
|
||||
#define PCI_INTERRUPT_LINE_MASK 0xff
|
||||
#define PCI_INTERRUPT_LINE(icr) \
|
||||
(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
|
||||
|
||||
#define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \
|
||||
((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
|
||||
(((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \
|
||||
(((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \
|
||||
(((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT))
|
||||
|
||||
#define PCI_INTERRUPT_PIN_NONE 0x00
|
||||
#define PCI_INTERRUPT_PIN_A 0x01
|
||||
#define PCI_INTERRUPT_PIN_B 0x02
|
||||
#define PCI_INTERRUPT_PIN_C 0x03
|
||||
#define PCI_INTERRUPT_PIN_D 0x04
|
||||
#define PCI_INTERRUPT_PIN_MAX 0x04
|
||||
|
||||
/* Header Type 1 (Bridge) configuration registers */
|
||||
#define PCI_BRIDGE_BUS_REG 0x18
|
||||
#define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0
|
||||
#define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8
|
||||
#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16
|
||||
|
||||
#define PCI_BRIDGE_STATIO_REG 0x1C
|
||||
#define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0
|
||||
#define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8
|
||||
#define PCI_BRIDGE_STATIO_STATUS_SHIFT 16
|
||||
#define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0
|
||||
#define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0
|
||||
#define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff
|
||||
#define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1)
|
||||
|
||||
#define PCI_BRIDGE_MEMORY_REG 0x20
|
||||
#define PCI_BRIDGE_MEMORY_BASE_SHIFT 4
|
||||
#define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20
|
||||
#define PCI_BRIDGE_MEMORY_BASE_MASK 0xffff
|
||||
#define PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff
|
||||
|
||||
#define PCI_BRIDGE_PREFETCHMEM_REG 0x24
|
||||
#define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4
|
||||
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20
|
||||
#define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff
|
||||
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff
|
||||
#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf)
|
||||
|
||||
#define PCI_BRIDGE_PREFETCHBASE32_REG 0x28
|
||||
#define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C
|
||||
|
||||
#define PCI_BRIDGE_IOHIGH_REG 0x30
|
||||
#define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0
|
||||
#define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16
|
||||
#define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff
|
||||
#define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff
|
||||
|
||||
#define PCI_BRIDGE_CONTROL_REG 0x3C
|
||||
#define PCI_BRIDGE_CONTROL_SHIFT 16
|
||||
#define PCI_BRIDGE_CONTROL_MASK 0xffff
|
||||
#define PCI_BRIDGE_CONTROL_PERE (1 << 0)
|
||||
#define PCI_BRIDGE_CONTROL_SERR (1 << 1)
|
||||
#define PCI_BRIDGE_CONTROL_ISA (1 << 2)
|
||||
#define PCI_BRIDGE_CONTROL_VGA (1 << 3)
|
||||
/* Reserved (1 << 4) */
|
||||
#define PCI_BRIDGE_CONTROL_MABRT (1 << 5)
|
||||
#define PCI_BRIDGE_CONTROL_SECBR (1 << 6)
|
||||
#define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7)
|
||||
#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8)
|
||||
#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9)
|
||||
#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10)
|
||||
#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11)
|
||||
/* Reserved (1 << 12) - (1 << 15) */
|
||||
|
||||
/*
|
||||
* Vital Product Data resource tags.
|
||||
*/
|
||||
struct pci_vpd_smallres {
|
||||
uint8_t vpdres_byte0; /* length of data + tag */
|
||||
/* Actual data. */
|
||||
} __attribute__((__packed__));
|
||||
|
||||
struct pci_vpd_largeres {
|
||||
uint8_t vpdres_byte0;
|
||||
uint8_t vpdres_len_lsb; /* length of data only */
|
||||
uint8_t vpdres_len_msb;
|
||||
/* Actual data. */
|
||||
} __attribute__((__packed__));
|
||||
|
||||
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
|
||||
|
||||
#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7)
|
||||
#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf)
|
||||
|
||||
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
|
||||
|
||||
#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */
|
||||
#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */
|
||||
#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */
|
||||
|
||||
#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */
|
||||
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
|
||||
|
||||
struct pci_vpd {
|
||||
uint8_t vpd_key0;
|
||||
uint8_t vpd_key1;
|
||||
uint8_t vpd_len; /* length of data only */
|
||||
/* Actual data. */
|
||||
} __attribute__((__packed__));
|
||||
|
||||
/*
|
||||
* Recommended VPD fields:
|
||||
*
|
||||
* PN Part number of assembly
|
||||
* FN FRU part number
|
||||
* EC EC level of assembly
|
||||
* MN Manufacture ID
|
||||
* SN Serial Number
|
||||
*
|
||||
* Conditionally recommended VPD fields:
|
||||
*
|
||||
* LI Load ID
|
||||
* RL ROM Level
|
||||
* RM Alterable ROM Level
|
||||
* NA Network Address
|
||||
* DD Device Driver Level
|
||||
* DG Diagnostic Level
|
||||
* LL Loadable Microcode Level
|
||||
* VI Vendor ID/Device ID
|
||||
* FU Function Number
|
||||
* SI Subsystem Vendor ID/Subsystem ID
|
||||
*
|
||||
* Additional VPD fields:
|
||||
*
|
||||
* Z0-ZZ User/Product Specific
|
||||
*/
|
||||
|
||||
/*
|
||||
* Threshold below which 32bit PCI DMA needs bouncing.
|
||||
*/
|
||||
#define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL
|
||||
|
||||
#endif /* _DEV_PCI_PCIREG_H_ */
|
||||
@@ -84,3 +84,14 @@ irq_setmask_8259A(uint16_t mask)
|
||||
cprintf("\n");
|
||||
}
|
||||
|
||||
void
|
||||
irq_eoi(void)
|
||||
{
|
||||
// OCW2: rse00xxx
|
||||
// r: rotate
|
||||
// s: specific
|
||||
// e: end-of-interrupt
|
||||
// xxx: specific interrupt line
|
||||
outb(IO_PIC1, 0x20);
|
||||
outb(IO_PIC2, 0x20);
|
||||
}
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
extern uint16_t irq_mask_8259A;
|
||||
void pic_init(void);
|
||||
void irq_setmask_8259A(uint16_t mask);
|
||||
void irq_eoi(void);
|
||||
#endif // !__ASSEMBLER__
|
||||
|
||||
#endif // !JOS_KERN_PICIRQ_H
|
||||
|
||||
@@ -11,6 +11,8 @@
|
||||
#include <kern/syscall.h>
|
||||
#include <kern/console.h>
|
||||
#include <kern/sched.h>
|
||||
#include <kern/time.h>
|
||||
#include <kern/e1000.h>
|
||||
|
||||
// Print a string to the system console.
|
||||
// The string is exactly 'len' characters long.
|
||||
@@ -55,11 +57,13 @@ sys_env_destroy(envid_t envid)
|
||||
|
||||
if ((r = envid2env(envid, &e, 1)) < 0)
|
||||
return r;
|
||||
|
||||
|
||||
if (e == curenv)
|
||||
cprintf("[%08x] exiting gracefully\n", curenv->env_id);
|
||||
else
|
||||
cprintf("[%08x] destroying %08x\n", curenv->env_id, e->env_id);
|
||||
|
||||
env_destroy(e);
|
||||
return 0;
|
||||
}
|
||||
@@ -430,6 +434,30 @@ sys_ipc_recv(void *dstva)
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Return the current time.
|
||||
static int
|
||||
sys_time_msec(void)
|
||||
{
|
||||
// LAB 6: Your code here.
|
||||
return time_msec();
|
||||
// panic("sys_time_msec not implemented");
|
||||
}
|
||||
|
||||
int
|
||||
sys_pkt_try_send(void * buf, size_t len)
|
||||
{
|
||||
user_mem_assert(curenv, buf, len, PTE_U);
|
||||
return e1000_transmit(buf, len);
|
||||
}
|
||||
|
||||
int
|
||||
sys_pkt_try_receive(void *rev_buf, size_t *len)
|
||||
{
|
||||
//cprintf("try recive...\n");
|
||||
return e1000_receive(rev_buf, len);
|
||||
}
|
||||
|
||||
|
||||
// Dispatches to the correct kernel function, passing the arguments.
|
||||
int32_t
|
||||
syscall(uint32_t syscallno, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5)
|
||||
@@ -472,6 +500,13 @@ syscall(uint32_t syscallno, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4,
|
||||
|
||||
case SYS_env_set_trapframe:
|
||||
return sys_env_set_trapframe((envid_t) a1, (struct Trapframe *) a2);
|
||||
case SYS_time_msec:
|
||||
return sys_time_msec();
|
||||
case SYS_pkt_try_send:
|
||||
return sys_pkt_try_send((void *) a1, (size_t) a2);
|
||||
case SYS_pkt_try_recv:
|
||||
return sys_pkt_try_receive((void *) a1, (size_t *) a2);
|
||||
|
||||
case NSYSCALLS:
|
||||
return -E_INVAL;
|
||||
|
||||
|
||||
26
lab/kern/time.c
Normal file
26
lab/kern/time.c
Normal file
@@ -0,0 +1,26 @@
|
||||
#include <kern/time.h>
|
||||
#include <inc/assert.h>
|
||||
|
||||
static unsigned int ticks;
|
||||
|
||||
void
|
||||
time_init(void)
|
||||
{
|
||||
ticks = 0;
|
||||
}
|
||||
|
||||
// This should be called once per timer interrupt. A timer interrupt
|
||||
// fires every 10 ms.
|
||||
void
|
||||
time_tick(void)
|
||||
{
|
||||
ticks++;
|
||||
if (ticks * 10 < ticks)
|
||||
panic("time_tick: time overflowed");
|
||||
}
|
||||
|
||||
unsigned int
|
||||
time_msec(void)
|
||||
{
|
||||
return ticks * 10;
|
||||
}
|
||||
11
lab/kern/time.h
Normal file
11
lab/kern/time.h
Normal file
@@ -0,0 +1,11 @@
|
||||
#ifndef JOS_KERN_TIME_H
|
||||
#define JOS_KERN_TIME_H
|
||||
#ifndef JOS_KERNEL
|
||||
# error "This is a JOS kernel header; user programs should not #include it"
|
||||
#endif
|
||||
|
||||
void time_init(void);
|
||||
void time_tick(void);
|
||||
unsigned int time_msec(void);
|
||||
|
||||
#endif /* JOS_KERN_TIME_H */
|
||||
@@ -13,6 +13,7 @@
|
||||
#include <kern/picirq.h>
|
||||
#include <kern/cpu.h>
|
||||
#include <kern/spinlock.h>
|
||||
#include <kern/time.h>
|
||||
|
||||
static struct Taskstate ts;
|
||||
|
||||
@@ -227,8 +228,6 @@ print_regs(struct PushRegs *regs)
|
||||
static void
|
||||
trap_dispatch(struct Trapframe *tf)
|
||||
{
|
||||
// Handle processor exceptions.
|
||||
// LAB 3: Your code here.
|
||||
switch(tf->tf_trapno) {
|
||||
case T_PGFLT:
|
||||
page_fault_handler(tf);
|
||||
@@ -251,6 +250,7 @@ trap_dispatch(struct Trapframe *tf)
|
||||
case (IRQ_OFFSET + IRQ_TIMER):
|
||||
// 回应8259A 接收中断。
|
||||
lapic_eoi();
|
||||
time_tick();
|
||||
sched_yield();
|
||||
break;
|
||||
|
||||
@@ -273,7 +273,6 @@ trap_dispatch(struct Trapframe *tf)
|
||||
return;
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user