mirror of
https://github.com/SmallPond/MIT6.828_OS.git
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136 lines
4.5 KiB
C
136 lines
4.5 KiB
C
#ifndef JOS_KERN_E1000_H
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#define JOS_KERN_E1000_H
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#include <inc/types.h>
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#define PCI_E1000_VENDER_ID 0x8086
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#define PCI_E1000_DEVICE_ID 0x100E
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/* 循环队列的长度*/
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#define TX_DESC_SIZE 32
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#define TX_PACKET_SIZE 2048
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#define RX_DESC_SIZE 128
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#define RX_PACKET_SIZE 2048
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/* Register Set
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*
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* RW - register is both readable and writable
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*
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*/
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#define E1000_DEVICE_STATUS 0x00008 /* Device Status - RO */
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#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
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#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
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#define E1000_RCTL 0x00100 /* RX Control - RW */
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#define E1000_TCTL 0x00400 /* TX Control - RW */
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#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
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#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
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#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
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#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
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#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
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#define E1000_RA 0x05400 /* Receive Address - RW Array */
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#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
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#define E1000_TDBAH 0X03804 /* TX Descriptor Base Address High - RW */
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#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
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#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
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#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
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#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
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/* Transmit Control */
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#define E1000_TCTL_RST 0x00000001 /* Reserved */
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#define E1000_TCTL_EN 0x00000002 /* enable tx */
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#define E1000_TCTL_BCE 0x00000004 /* Reserved */
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#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
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#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
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#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
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#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
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#define E1000_TCTL_PBE 0x00800000 /* Reserved */
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#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
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#define E1000_TCTL_MULR 0x10000000 /* Reserved */
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#define E1000_RCTL_EN 0x00000002 /* enable */
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#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
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#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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/* Transmit Descriptor */
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struct E1000TxDesc {
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uint64_t buffer_addr; /* Address of the descriptor's data buffer */
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uint16_t length; /* Data buffer length */
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uint8_t cso; /* Checksum offset */
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uint8_t cmd; /* Descriptor control */
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uint8_t status; /* Descriptor status */
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uint8_t css; /* Checksum start */
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uint16_t special;
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}__attribute__((packed));
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/* Transmit Descriptor bit definitions */
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#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
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#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
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#define E1000_TXD_CMD_EOP 0x01 /* End of Packet */
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#define E1000_TXD_CMD_RS 0x08 /* Report Status */
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#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
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#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
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#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
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#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
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#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
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/* Receive Descriptor */
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struct E1000RxDesc {
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uint64_t buffer_addr;
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uint16_t length; /* Data buffer length */
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uint16_t chksum; /* Check Sum */
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uint8_t status;
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uint8_t err;
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uint16_t special;
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};
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/* Transmit Descriptor bit definitions */
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#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
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#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
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#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
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#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
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#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
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#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
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#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
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/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
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#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
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#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
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#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
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int e1000_transmit(void *addr, size_t len);
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int e1000_receive(void *buf, size_t *len);
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#endif // SOL >= 6
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