add os[1-8]-ref for os refereces, add guide, add README

guide/source/appendix-d/index.rst

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+附录 D：RISC-V相关信息
+=================================================
+
+RISCV汇编相关
+-----------------------------------------------
+
+- `RISC-V Assembly Programmer's Manual  <https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md>`_ 
+- `RISC-V Low-level Test Suits <https://github.com/riscv/riscv-tests>`_
+- `CoreMark®-PRO comprehensive, advanced processor benchmark <https://github.com/RISCVERS/coremark-pro>`_ 
+- `riscv-tests的使用 <https://stackoverflow.com/questions/39321554/how-do-i-use-the-riscv-tests-suite>`_
+
+RISCV硬件相关
+-----------------------------------------------
+
+Quick Reference
+
+- `Registers & ABI <https://five-embeddev.com/quickref/regs_abi.html>`_ 
+- `Interrupt <https://five-embeddev.com/quickref/interrupts.html>`_ 
+- `ISA & Extensions <https://five-embeddev.com/quickref/isa_ext.html>`_ 
+- `Toolchain <https://five-embeddev.com/quickref/tools.html>`_ 
+- `Control and Status Registers (CSRs) <https://five-embeddev.com/quickref/csrs.html>`_ 
+- `Accessing CSRs <https://five-embeddev.com/quickref/csrs-access.html>`_ 
+- `Assembler & Instructions <https://five-embeddev.com/quickref/instructions.html>`_ 
+
+ISA
+
+- `User-Level ISA, Version 1.12 <https://five-embeddev.com/riscv-isa-manual/latest/riscv-spec.html>`_ 
+- `4 Supervisor-Level ISA, Version 1.12 <https://five-embeddev.com/riscv-isa-manual/latest/supervisor.html>`_ 
+- `Vector Extension <https://five-embeddev.com/riscv-v-spec/draft/v-spec.html>`_ 
+- `RISC-V Bitmanip Extension <https://five-embeddev.com/riscv-bitmanip/draft/bitmanip.html>`_ 
+- `External Debug  <https://five-embeddev.com/riscv-debug-spec/latest/riscv-debug-spec.html>`_ 
+- `ISA Resources <https://five-embeddev.com/riscv-isa-manual/>`_