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32 lines
1.7 KiB
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32 lines
1.7 KiB
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附录 D：RISC-V相关信息
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=================================================
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RISCV汇编相关
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-----------------------------------------------
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- `RISC-V Assembly Programmer's Manual <https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md>`_
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- `RISC-V Low-level Test Suits <https://github.com/riscv/riscv-tests>`_
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- `CoreMark®-PRO comprehensive, advanced processor benchmark <https://github.com/RISCVERS/coremark-pro>`_
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- `riscv-tests的使用 <https://stackoverflow.com/questions/39321554/how-do-i-use-the-riscv-tests-suite>`_
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RISCV硬件相关
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-----------------------------------------------
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Quick Reference
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- `Registers & ABI <https://five-embeddev.com/quickref/regs_abi.html>`_
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- `Interrupt <https://five-embeddev.com/quickref/interrupts.html>`_
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- `ISA & Extensions <https://five-embeddev.com/quickref/isa_ext.html>`_
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- `Toolchain <https://five-embeddev.com/quickref/tools.html>`_
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- `Control and Status Registers (CSRs) <https://five-embeddev.com/quickref/csrs.html>`_
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- `Accessing CSRs <https://five-embeddev.com/quickref/csrs-access.html>`_
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- `Assembler & Instructions <https://five-embeddev.com/quickref/instructions.html>`_
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ISA
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- `User-Level ISA, Version 1.12 <https://five-embeddev.com/riscv-isa-manual/latest/riscv-spec.html>`_
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- `4 Supervisor-Level ISA, Version 1.12 <https://five-embeddev.com/riscv-isa-manual/latest/supervisor.html>`_
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- `Vector Extension <https://five-embeddev.com/riscv-v-spec/draft/v-spec.html>`_
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- `RISC-V Bitmanip Extension <https://five-embeddev.com/riscv-bitmanip/draft/bitmanip.html>`_
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- `External Debug <https://five-embeddev.com/riscv-debug-spec/latest/riscv-debug-spec.html>`_
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- `ISA Resources <https://five-embeddev.com/riscv-isa-manual/>`_ |