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@@ -137,26 +137,26 @@ Namespaces</h2></td></tr>
Functions</h2></td></tr>
<tr class="memitem:a24d21a345ed06f7fba6919718cf3e058"><td class="memTemplParams" colspan="2">template&lt;typename T &gt; </td></tr>
<tr class="memitem:a24d21a345ed06f7fba6919718cf3e058"><td class="memTemplItemLeft" align="right" valign="top">void&#160;</td><td class="memTemplItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#a24d21a345ed06f7fba6919718cf3e058">lru_tests::log</a> (T msg)</td></tr>
<tr class="memdesc:a24d21a345ed06f7fba6919718cf3e058"><td class="mdescLeft">&#160;</td><td class="mdescRight">A function to print given message on console. <a href="../../d3/db3/lru__cache_8cpp.html#a24d21a345ed06f7fba6919718cf3e058">More...</a><br /></td></tr>
<tr class="memdesc:a24d21a345ed06f7fba6919718cf3e058"><td class="mdescLeft">&#160;</td><td class="mdescRight">A function to print given message on console. <br /></td></tr>
<tr class="separator:a24d21a345ed06f7fba6919718cf3e058"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6401e8f2d41d8cc9cd0e52ab381608d4"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#a6401e8f2d41d8cc9cd0e52ab381608d4">lru_tests::test_1</a> ()</td></tr>
<tr class="memdesc:a6401e8f2d41d8cc9cd0e52ab381608d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">A simple test case The assert statement will check expected hist and miss to resultant hits and miss. <a href="../../d3/db3/lru__cache_8cpp.html#a6401e8f2d41d8cc9cd0e52ab381608d4">More...</a><br /></td></tr>
<tr class="memdesc:a6401e8f2d41d8cc9cd0e52ab381608d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">A simple test case The assert statement will check expected hist and miss to resultant hits and miss. <br /></td></tr>
<tr class="separator:a6401e8f2d41d8cc9cd0e52ab381608d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b02e288a407876a8d6024f98a2a25ec"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#a4b02e288a407876a8d6024f98a2a25ec">lru_tests::test_2</a> ()</td></tr>
<tr class="memdesc:a4b02e288a407876a8d6024f98a2a25ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">A test case contains hits more than cache size The assert statement will check expected hist and miss to resultant hits and miss. <a href="../../d3/db3/lru__cache_8cpp.html#a4b02e288a407876a8d6024f98a2a25ec">More...</a><br /></td></tr>
<tr class="memdesc:a4b02e288a407876a8d6024f98a2a25ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">A test case contains hits more than cache size The assert statement will check expected hist and miss to resultant hits and miss. <br /></td></tr>
<tr class="separator:a4b02e288a407876a8d6024f98a2a25ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a01ec21fc91ddafd964ae2035ba7892c0"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#a01ec21fc91ddafd964ae2035ba7892c0">lru_tests::test_3</a> ()</td></tr>
<tr class="memdesc:a01ec21fc91ddafd964ae2035ba7892c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">A simple test case The assert statement will check expected hist and miss to resultant hits and miss. <a href="../../d3/db3/lru__cache_8cpp.html#a01ec21fc91ddafd964ae2035ba7892c0">More...</a><br /></td></tr>
<tr class="memdesc:a01ec21fc91ddafd964ae2035ba7892c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">A simple test case The assert statement will check expected hist and miss to resultant hits and miss. <br /></td></tr>
<tr class="separator:a01ec21fc91ddafd964ae2035ba7892c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a3be6d8871b1f5dc03688da8f3ee9e6"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#a6a3be6d8871b1f5dc03688da8f3ee9e6">lru_tests::run_tests</a> ()</td></tr>
<tr class="memdesc:a6a3be6d8871b1f5dc03688da8f3ee9e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">A function to invoke all test cases. <a href="../../d3/db3/lru__cache_8cpp.html#a6a3be6d8871b1f5dc03688da8f3ee9e6">More...</a><br /></td></tr>
<tr class="memdesc:a6a3be6d8871b1f5dc03688da8f3ee9e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">A function to invoke all test cases. <br /></td></tr>
<tr class="separator:a6a3be6d8871b1f5dc03688da8f3ee9e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="../../d3/db3/lru__cache_8cpp.html#ae66f6b31b5ad750f1fe042a706a4e3d4">main</a> ()</td></tr>
<tr class="memdesc:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Main function. <a href="../../d3/db3/lru__cache_8cpp.html#ae66f6b31b5ad750f1fe042a706a4e3d4">More...</a><br /></td></tr>
<tr class="memdesc:ae66f6b31b5ad750f1fe042a706a4e3d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Main function. <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p >An implementation of <a href="https://en.wikipedia.org/wiki/Cache_replacement_policies#Least_recently_used_(LRU)" target="_blank">LRU Cache</a>. Lru is a part of cache algorithms (also frequently called cache replacement algorithms or cache replacement policies). </p>
<div class="textblock"><p>An implementation of <a href="https://en.wikipedia.org/wiki/Cache_replacement_policies#Least_recently_used_(LRU)" target="_blank">LRU Cache</a>. Lru is a part of cache algorithms (also frequently called cache replacement algorithms or cache replacement policies). </p>
<h3><a class="anchor" id="autotoc_md95"></a>
Logic</h3>
<ul>
@@ -167,7 +167,7 @@ Logic</h3>
</ul>
<h3><a class="anchor" id="autotoc_md96"></a>
Algorithm explanation</h3>
<p >For a cache of page frame x:</p><ul>
<p>For a cache of page frame x:</p><ul>
<li>Check if the page is present in cache.</li>
<li>If not present, then check is the cache is full or not:</li>
<li>If the cache is full, REMOVE the last element from the cache.</li>
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</ul>
</li>
</ul>
<p >Every time a requested page is not found in cache, that is a miss or page fault, and if the page is present in cache, then its a hit.</p>
<p>Every time a requested page is not found in cache, that is a miss or page fault, and if the page is present in cache, then its a hit.</p>
<h2><a class="anchor" id="autotoc_md97"></a>
Data Structure used</h2>
<ul>
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