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====== b43 ======
Created Sunday 05 August 2012
Broadcom的BCM9 4318MPG系列miniPCI网卡，需要在kernel中编译相应的驱动，同时还要使用固件。
驱动位于kernel中的wireless menu中，固件需要单独下载。注意，firmware是由网卡芯片执行的，所以
与CPU体系结构无关，只需将其放到目标板的/lib/firmware/b43目录下即可(最后需要运行./ltib --config命令重新生
成rootfs.ext2.gz.uboot目录)。
broadcom的firmware按一下方法安装：
wget http://bues.ch/b43/fwcutter/b43-fwcutter-015.tar.bz2
tar xvf b43-fwcutter-015.tar.bz2
cd b43-fwcutter-015/
make
sudo make install #安装fwcutter工具到host中
cd ..
export FIRMWARE_INSTALL_DIR="/lib/firmware"
wget http://www.lwfinger.com/b43-firmware/broadcom-wl-5.100.138.tar.bz2
tar xvf broadcom-wl-5.100.138.tar.bz2
sudo b43-fwcutter -w "$FIRMWARE_INSTALL_DIR" broadcom-wl-5.100.138/linux/wl_apsta.o
ls /lib/firmware/b43/
sudo chmod -R 755 /lib/firmware/b43/
ls /lib/firmware/b43/
sudo mkdir -p ~/PPC/ltib-mpc8315erdb-20100719/rootfs/lib/firmware/b43
sudo cp /lib/firmware/b43/{bog*,ucode5.fw} [[~/PPC/ltib-mpc8315erdb-20100719/rootfs/lib/firmware/b43]]

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====== 下载错误 ======
Created Tuesday 21 February 2012

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====== Bad Data CRC ======
Created Tuesday 21 February 2012
http://e2e.ti.com/support/embedded/linux/f/354/t/43146.aspx
解决方法：将主机的MTU设为大于1468如1500即可：
# ifconfig eth0 mtu 1500
-------------------------------------------------
Hi Tim,
Thanks for debugging this.
The only way forward here is to use wireshark or an equivalent network sniffer on the TFTP host and see what could __be wrong with the transfers__.
Looking at the data my guess is that __your host ethernet card is unable to handle MTU sized packets__. Note that I am still suspecting the host only because I haven't seen this problem on my setup nor see widespread complaints regarding this issue.
The 0x5BC in your analysis corresponds to 1468 which is what seems to be presented as block size option to the server:
96 /* 512 is poor choice for ethernet, **MTU is typically 1500.**
97 * Minus eth.hdrs thats __1468__. Can get 2x better throughput with
98 * almost-MTU block sizes. At least try... fall back to 512 if need be.
99 * (but those using CONFIG_IP_DEFRAG may want to set a larger block in cfg file)
100 */
101 #ifdef CONFIG_TFTP_BLOCKSIZE
102 #define TFTP_MTU_BLOCKSIZE CONFIG_TFTP_BLOCKSIZE
103 #else
104 #define TFTP_MTU_BLOCKSIZE __1468__
105#endif
Looking further into the code, it looks like this value can be overridden using the __"tftpblocksize"__ environment variable. Can you please set this variable to something lower say 1024 bytes and try tftp again?
Thanks,
Sekhar
---------------------------------------------------
Hey Sekhar & Anshuman:
We finally got this resolved. __It had to do with the MTU packet size in the u-boot image being set to 1468__. I was using a value of 1300 on my PC. To fix this, I did the following:
In the u-boot srouce code directory, I changed the file (__net/tftp.c__) in the u-boot source directory from:
#define TFTP_MTU_BLOCKSIZE 1468
static unsigned short TftpBlkSize=TFTP_BLOCK_SIZE;
static unsigned short TftpBlkSizeOption=TFTP_MTU_BLOCKSIZE;
to:
#define TFTP_MTU_BLOCKSIZE __1024__
static unsigned short TftpBlkSize=TFTP_BLOCK_SIZE;
static unsigned short TftpBlkSizeOption=TFTP_MTU_BLOCKSIZE;
and then rebuilt u-boot using the following:
make distclean
make **davinci_dm365_evm_config**
make
I used CCS to reflash the u-boot file on my FLASH on the board and then powered up the board using my Windows XP TFTP server and my VMWare Linux TFTP server and it worked just fine. Looks like the MTU packet size was different on the DM365 EVM relative to what I was using with my DM6446 and DM6467 and DM6467T EVMs. The MTU packet size on my PC was set at 1300__ to force it to use smaller packet sizes __from previous work I was doing with multicasting of video and needed smaller packet sizes to minimize packet losses.

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====== chosen node create failed ======
Created Tuesday 21 February 2012
http://www.embeddedlinuxprimer.com/dtc
===== Using Device Tree Compiler =====
Get the dtc compiler and build it:
From your favorite working directory:
$ git clone git://git.kernel.org/pub/scm/linux/kernel/git/galak/dtc.git
$ cd dtc
$ make
$ sudo make install
To generate dtb source from the binary blob (dtb)
**$ dtc -I dtb -O dts /tftpboot/mpc8349.dtb >/tftpboot/mpc8349.dts**
To generate the dtb binary blob from source:
$ **dtc -O dtb arch/powerpc/boot/dts/mpc8349emitx.dts -S 20000 > /tftpboot/mpc8349emitx.dtb**
-S argument sets some spare space for the u-boot to add /choosen (and
some other) nodes.
------------------------------------------------------------------------
By challinan at 2008-11-26 08:29
Login or register to post comments
===== U-Boot Error: /chosen node create failed =====
If you get an error like this when you try to boot a kernel using U-Boot:
ERROR: /chosen node create failed - must RESET the board to recover.
It generally means that you __need to add some padding to your device tree binary__ (blob!). U-Boot tries to create nodes in your dtb, and if there is no room to create these nodes, it fails with an error similar to this one.
__Use -S as above__, to add additional padding to the dtb.
注意，只使用-S参数是不行的，还要指定-R 参数。如下：
# __dtc -I dts -O dtb -R 8 -S 20000 mpc8315erdb-default.dts >mpc8315erdb-default.dtb__
注意：上面的命令必须在root环境下运行(sudo不合适)，因为dtc是一个脚本。
from：
http://lists.denx.de/pipermail/u-boot/2007-December/027167.html

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Creation-Date: 2012-02-20T21:11:32+08:00
====== u-boot ======
Created Monday 20 February 2012
Filesystem stats, including padding:
Total size = 16028k
Total number of files = 605
Your ramdisk exceeds the old default size of 4096k, you may need to
set the command line argument for ramdisk_size in your bootloader
allowing 10% free this gives 17630k . For instance, for u-boot:
setenv bootargs root=/dev/ram rw ramdisk_size=17630
creating an ext2 compressed filesystem image: rootfs.ext2.gz
genext2fs: Running in LTIB backwards compatibility mode: -i -> -N
creating a uboot ramdisk image: rootfs.ext2.gz.uboot
Image Name: uboot ext2 ramdisk rootfs
Created: Mon Feb 20 20:47:49 2012
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 4764328 Bytes = 4652.66 kB = 4.54 MB
Load Address: 0x00000000
Entry Point: 0x00000000
Started: Mon Feb 20 20:40:22 2012
Ended: Mon Feb 20 20:47:49 2012
Elapsed: 447 seconds
Build Succeeded
==============3.1.8内核====================
WARN: /home/geekard/ppc/ltib-mpc8315erdb-20100719/rootfs.tmp/sbin/sln statically linked
WARN: /home/geekard/ppc/ltib-mpc8315erdb-20100719/rootfs.tmp/sbin/ldconfig statically linked
Filesystem stats, including padding:
Total size = 56860k
Total number of files = 885
Your ramdisk exceeds the old default size of 4096k, you may need to
set the command line argument for ramdisk_size in your bootloader
allowing 10% free this gives 62546k . For instance, for u-boot:
setenv bootargs root=/dev/ram rw ramdisk_size=62546
creating an ext2 compressed filesystem image: rootfs.ext2.gz
genext2fs: Running in LTIB backwards compatibility mode: -i -> -N
creating a uboot ramdisk image: rootfs.ext2.gz.uboot
Image Name: uboot ext2 ramdisk rootfs
Created: Tue Feb 21 17:07:03 2012
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 13446544 Bytes = 13131.39 kB = 12.82 MB
Load Address: 0x00000000
Entry Point: 0x00000000
Started: Tue Feb 21 17:04:48 2012
Ended: Tue Feb 21 17:07:03 2012
Elapsed: 135 seconds
Build Succeeded
== ============latest(/tftp.bak)======== ==
setenv bootargs root=/dev/ram rw ramdisk_size=61586
== ===========latest(/tftp)============ ==
setenv bootargs root=/dev/ram rw ramdisk_size=66959
== ====latest(libnl)================= ==
setenv bootargs root=/dev/ram rw ramdisk_size=67337
== latest(iw)=================== ==
setenv bootargs root=/dev/ram rw ramdisk_size=67460
== ========crda====== ==
setenv bootargs root=/dev/ram rw ramdisk_size=68613

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Creation-Date: 2012-02-22T11:36:40+08:00
====== 启动相关 ======
Created Wednesday 22 February 2012

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Creation-Date: 2012-08-05T13:14:27+08:00
====== ath5k dump ======
Created Sunday 05 August 2012
[root@mpc8315erdb /home]#
irq 48: nobody cared (try booting with the "irqpoll" option)
Call Trace:
[dfff7f00] [c0007ac8] 0xc0007ac8 (unreliable)
[dfff7f40] [c0054b58] 0xc0054b58
[dfff7f60] [c0054e98] 0xc0054e98
[dfff7f90] [c0052ec4] 0xc0052ec4
[dfff7fd0] [c0052ff0] 0xc0052ff0
[dfff7fe0] [c00555c8] 0xc00555c8
[dfff7ff0] [c000cd3c] 0xc000cd3c
[c03b3eb0] [c0005534] 0xc0005534
[c03b3ee0] [c000eb80] 0xc000eb80
--- Exception: 501 at 0xc00085c8
LR = 0xc00085c8
[c03b3fa0] [c0008590] 0xc0008590 (unreliable)
[c03b3fc0] [c036d7a0] 0xc036d7a0
[c03b3ff0] [00003438] 0x003438
handlers:
[<e199ba00>] 0xe199ba00
__Disabling IRQ #48__
[root@mpc8315erdb /home]#
这是由于PCB板子上的中断线是漏极开漏的，但是没有加上拉电阻，这样就一直处于低电平。
kernel启动后，认为是外部产生的中断，所以执行ath5k的中断代码，该代码会查找设备的中断状态
寄存器，但是读到的值为空(因为设备其实并没有产生中断)。所以提示nobody cared。

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====== uboot bdinfo输出的memsize不对 ======
Created Friday 03 August 2012
这是由于comm/cmd_bdinfo.c中的print_lnum("memsize", bd->bi_memsize)使用的是64位的printf。需要将printf_lnum改为print_num()即可。
这个错误并不致命，修改与否都可以。

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====== 内核不输出启动信息 ======
Created Wednesday 22 February 2012
这可能与uboot的环境变量bootargs中console设置错误有关，正确的应该为：
setenv bootargs root=/dev/ram rw console=ttyS0,115200 ramdisk_size=xxxx
注意：ramdisk_size大小要和ltib输出的一致，但可以比后者大，否则kernel启动的最后
在mount该文件时，会出错。

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====== 调用ifconfig设置进行IP地址的设置提示Cannot assign requested address ======
Created Wednesday 22 February 2012
http://hi.baidu.com/wang_jianguang/blog/item/e6d4904c9e0ecd3aaec3abdb.html
Linux昨天晚上终于跑起来了，文件系统也可以用了，我在开机时调用ifconfig设置进行IP地址的设置，可是总是会显示：
ifconfig: SIOCSIFFLAGS: Cannot assign requested address
很纳闷，网上查了一下，__原来是MAC地址的问题__，经过以下的处理，就OK啦~
# ifconfig eth0 down
# ifconfig eth0 hw ether 00:00:AA:BB:CC:DD
# ifconfig eth0 up
eth0: link down
# ifeth0: link up, 100Mbps, full-duplex, lpa 0xCDE1

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====== 编译错误 ======
Created Tuesday 21 February 2012

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====== busybox ======
Created Saturday 04 August 2012
1. 在编译老版本的busybox时，出现：
+ make menuconfig 'HOSTCC=ccache /usr/bin/gcc -B/usr/bin/'
Makefile:421: *** mixed implicit and normal rules. Stop.
error: Bad exit status from /home/geekard/PPC/ltib-mpc8315erdb-20100719/tmp/rpm-tmp.23736 (%build)
这是由于make工具版本太高的原因，可以降级make为3.8.1或者升级busybox到最新版。我们__采用后者__方法。
2.下载最新版busybox。
[geekard@kb310 ltib-mpc8315erdb-20100719]$ rm -rf rpm/BUILD/busybox-1.11.2/*
[geekard@kb310 ltib-mpc8315erdb-20100719]$ rm -rf tmp/*
[geekard@kb310 ltib-mpc8315erdb-20100719]$ cp -r modify/busybox-1.20.2/* rpm/BUILD/busybox-1.11.2/
[geekard@kb310 ltib-mpc8315erdb-20100719]$ [[./ltib]] --config #注意，在package list中选中configure busybox at build time
3. 编译时出错：
loginutils/passwd.c: In function 'passwd_main':
loginutils/passwd.c:104:16: error: storage size of 'rlimit_fsize' isn't known
loginutils/passwd.c:188:2: warning: implicit declaration of function 'setrlimit' [-Wimplicit-function-declaration]
loginutils/passwd.c:188:12: error: 'RLIMIT_FSIZE' undeclared (first use in this function)
loginutils/passwd.c:188:12: note: each undeclared identifier is reported only once for each function it appears in
loginutils/passwd.c:104:16: warning: unused variable 'rlimit_fsize' [-Wunused-variable]
make[1]: *** [loginutils/passwd.o] Error 1
make: *** [loginutils] Error 2
make: *** Waiting for unfinished jobs....
-------------------------------------------------------------------
http://lists.busybox.net/pipermail/busybox/2012-May/077766.html
Fix this by including sys/resource.h.
Signed-off-by: Markus Trippelsdorf <markus at trippelsdorf.de>
---
include/libbb.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/libbb.h b/include/libbb.h
index f12800f..e7806c2 100644
--- a/include/libbb.h
+++ b/include/libbb.h
@@ -40,6 +40,7 @@
#include <sys/poll.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
+#include <sys/resource.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <sys/time.h>
--
Markus
------------------------------
4. 提示找不到rpc/rpc.h文件：
util-linux/mount.c:134:22: fatal error: rpc/rpc.h: No such file or directory
compilation terminated.
make[1]: *** [util-linux/mount.o] Error 1
make: *** [util-linux] Error 2
error: Bad exit status from /home/geekard/PPC/ltib-mpc8315erdb-20100719/tmp/rpm-tmp.84999 (%build)
这是由于glibc>2.16后将SUN RPC系列组件从glibc中删除了，代之的是librpc项目库。解决方式是去掉mount命令的NFS文件类型选项。
Linux System Utilities —> [ ] mout support NFS filesystem on linux

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====== crdb ======
Created Sunday 05 August 2012
在编译kernel时需要选中Network Supporting-->Wireless中的：
[*] use statically compiled regulatory rules database
该database文件可以用git获取：
git clone git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-regdb.git
目录中的db.txt即为database文件。然后将该文件复制到kernel的net/wiress目录中，然后重新编译kernle即可：
[geekard@kb310 ltib-mpc8315erdb-20100719]$ cp db.txt ~/PPC/source/linux-3.4.7/net/wireless/
附：
[[./db001.txt]]

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# This is the world regulatory domain
country 00:
(2402 - 2472 @ 40), (3, 20)
# Channel 12 - 13. No HT40 channel fits here
(2457 - 2482 @ 20), (3, 20), PASSIVE-SCAN, NO-IBSS
# Channel 14. Only JP enables this and for 802.11b only
(2474 - 2494 @ 20), (3, 20), PASSIVE-SCAN, NO-IBSS, NO-OFDM
# Channel 36 - 48
(5170 - 5250 @ 40), (3, 20), PASSIVE-SCAN, NO-IBSS
# NB: 5260 MHz - 5700 MHz requies DFS
# Channel 149 - 165
(5735 - 5835 @ 40), (3, 20), PASSIVE-SCAN, NO-IBSS
country AE:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AL:
(2402 - 2482 @ 20), (N/A, 20)
country AM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 18)
(5250 - 5330 @ 20), (N/A, 18), DFS
country AN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country AT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AU:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country AW:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AZ:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country BA: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BB:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country BD:
(2402 - 2482 @ 40), (N/A, 20)
country BE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BG: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 23)
(5250 - 5290 @ 40), (N/A, 23), DFS
(5490 - 5710 @ 40), (N/A, 30), DFS
country BH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
(5735 - 5835 @ 20), (N/A, 20)
country BL:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country BN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 30)
country BO:
(2402 - 2482 @ 40), (N/A, 30)
(5735 - 5835 @ 40), (N/A, 30)
country BR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country BY:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BZ:
(2402 - 2482 @ 40), (N/A, 30)
(5735 - 5835 @ 40), (N/A, 30)
country CA:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country CH: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country CL:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country CN:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
(5850 - 5930 @ 20), (N/A, 30)
country CO:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country CR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country CS:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country CY: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
# Data from http://www.ctu.eu/164/download/VOR/VOR-12-08-2005-34.pdf
# and http://www.ctu.eu/164/download/VOR/VOR-12-05-2007-6-AN.pdf
# Power at 5250 - 5350 MHz and 5470 - 5725 MHz can be doubled if TPC is
# implemented.
country CZ: DFS-ETSI
(2400 - 2483.5 @ 40), (N/A, 100 mW)
(5150 - 5250 @ 40), (N/A, 200 mW), NO-OUTDOOR
(5250 - 5350 @ 40), (N/A, 100 mW), NO-OUTDOOR, DFS
(5470 - 5725 @ 40), (N/A, 500 mW), DFS
# Data from "Frequenznutzungsplan" (as published in April 2008), downloaded from
# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38448/publicationFile/2659/Frequenznutzungsplan2008_Id17448pdf.pdf
# For the 5GHz range also see
# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38216/publicationFile/6579/WLAN5GHzVfg7_2010_28042010pdf.pdf
# The values have been reduced by a factor of 2 (3db) for non TPC devices
# (in other words: devices with TPC can use twice the tx power of this table).
# Note that the docs do not require TPC for 5150--5250; the reduction to
# 100mW thus is not strictly required -- however the conservative 100mW
# limit is used here as the non-interference with radar and satellite
# apps relies on the attenuation by the building walls only in the
# absence of DFS; the neighbour countries have 100mW limit here as well.
country DE: DFS-ETSI
# entries 279004 and 280006
(2400 - 2483.5 @ 40), (N/A, 100 mW)
# entry 303005
(5150 - 5250 @ 40), (N/A, 100 mW), NO-OUTDOOR
# entries 304002 and 305002
(5250 - 5350 @ 40), (N/A, 100 mW), NO-OUTDOOR, DFS
# entries 308002, 309001 and 310003
(5470 - 5725 @ 40), (N/A, 500 mW), DFS
country DK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country DO:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country DZ:
(2402 - 2482 @ 40), (N/A, 20)
country EC:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country EE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country EG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country ES: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country FI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country FR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GE:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country GB: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GD:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country GR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
(5490 - 5710 @ 20), (N/A, 27), DFS
country GT:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country GU:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country HN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country HK:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country HR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country HT:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country HU: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country ID:
(2402 - 2482 @ 40), (N/A, 20)
country IE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country IL:
(2402 - 2482 @ 40), (N/A, 20)
(5150 - 5250 @ 40), (N/A, 200 mW), NO-OUTDOOR
(5250 - 5350 @ 40), (N/A, 200 mW), NO-OUTDOOR, DFS
country IN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country IS: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country IR:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country IT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country JM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country JP:
(2402 - 2472 @ 40), (N/A, 20)
(2457 - 2482 @ 20), (N/A, 20)
(2474 - 2494 @ 20), (N/A, 20), NO-OFDM
(4910 - 4930 @ 10), (N/A, 23)
(4910 - 4990 @ 40), (N/A, 23)
(4930 - 4950 @ 10), (N/A, 23)
(5030 - 5045 @ 10), (N/A, 23)
(5030 - 5090 @ 40), (N/A, 23)
(5050 - 5060 @ 10), (N/A, 23)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 23), DFS
country JO:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
country KE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country KH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country KP:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5330 @ 40), (3, 20)
(5160 - 5250 @ 40), (3, 20), DFS
(5490 - 5630 @ 40), (3, 30), DFS
(5735 - 5815 @ 40), (3, 30)
country KR:
(2402 - 2482 @ 20), (N/A, 20)
(5170 - 5250 @ 20), (3, 20)
(5250 - 5330 @ 20), (3, 20), DFS
(5490 - 5630 @ 20), (3, 30), DFS
(5735 - 5815 @ 20), (3, 30)
country KW:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
country KZ:
(2402 - 2482 @ 40), (N/A, 20)
country LB:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country LI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LK:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 20), DFS
(5490 - 5710 @ 20), (3, 20), DFS
(5735 - 5835 @ 20), (3, 30)
country LT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LU: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LV: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MC: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country MA:
(2402 - 2482 @ 40), (N/A, 20)
country MO:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country MK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MY:
(2402 - 2482 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 30), DFS
(5735 - 5835 @ 40), (N/A, 30)
country MX:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country NL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20), NO-OUTDOOR
(5250 - 5330 @ 40), (N/A, 20), NO-OUTDOOR, DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country NO: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country NP:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country NZ:
(2402 - 2482 @ 40), (N/A, 30)
(5170 - 5250 @ 20), (3, 23)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country OM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country PA:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country PE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country PH:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PK:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country PT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country PR:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country QA:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country RO: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country RU:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 20), (N/A, 30)
country RW:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country SA:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 23)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country SE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country SI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SV:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country SY:
(2402 - 2482 @ 40), (N/A, 20)
country TW:
(2402 - 2472 @ 40), (3, 27)
(5270 - 5330 @ 40), (3, 17), DFS
(5735 - 5815 @ 40), (3, 30)
country TH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country TT:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country TN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country TR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country UA:
(2402 - 2482 @ 40), (N/A, 20)
country US: DFS-FCC
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5600 @ 40), (3, 20), DFS
(5650 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country UY:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country UZ:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country VE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5815 @ 40), (N/A, 23)
country VN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
country YE:
(2402 - 2482 @ 40), (N/A, 20)
country ZA:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country ZW:
(2402 - 2482 @ 40), (N/A, 20)

702
Zim/Research/Error_Notes/编译错误/crdb/db001.txt Normal file
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@@ -0,0 +1,702 @@
# This is the world regulatory domain
country 00:
(2402 - 2472 @ 40), (3, 20)
# Channel 12 - 13. No HT40 channel fits here
(2457 - 2482 @ 20), (3, 20), PASSIVE-SCAN, NO-IBSS
# Channel 14. Only JP enables this and for 802.11b only
(2474 - 2494 @ 20), (3, 20), PASSIVE-SCAN, NO-IBSS, NO-OFDM
# Channel 36 - 48
(5170 - 5250 @ 40), (3, 20), PASSIVE-SCAN, NO-IBSS
# NB: 5260 MHz - 5700 MHz requies DFS
# Channel 149 - 165
(5735 - 5835 @ 40), (3, 20), PASSIVE-SCAN, NO-IBSS
country AE:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AL:
(2402 - 2482 @ 20), (N/A, 20)
country AM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 18)
(5250 - 5330 @ 20), (N/A, 18), DFS
country AN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country AT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AU:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country AW:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country AZ:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country BA: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BB:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country BD:
(2402 - 2482 @ 40), (N/A, 20)
country BE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BG: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 23)
(5250 - 5290 @ 40), (N/A, 23), DFS
(5490 - 5710 @ 40), (N/A, 30), DFS
country BH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
(5735 - 5835 @ 20), (N/A, 20)
country BL:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country BN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 30)
country BO:
(2402 - 2482 @ 40), (N/A, 30)
(5735 - 5835 @ 40), (N/A, 30)
country BR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country BY:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country BZ:
(2402 - 2482 @ 40), (N/A, 30)
(5735 - 5835 @ 40), (N/A, 30)
country CA:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country CH: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country CL:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country CN:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
(5850 - 5930 @ 20), (N/A, 30)
country CO:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country CR:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country CS:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country CY: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
# Data from http://www.ctu.eu/164/download/VOR/VOR-12-08-2005-34.pdf
# and http://www.ctu.eu/164/download/VOR/VOR-12-05-2007-6-AN.pdf
# Power at 5250 - 5350 MHz and 5470 - 5725 MHz can be doubled if TPC is
# implemented.
country CZ: DFS-ETSI
(2400 - 2483.5 @ 40), (N/A, 100 mW)
(5150 - 5250 @ 40), (N/A, 200 mW), NO-OUTDOOR
(5250 - 5350 @ 40), (N/A, 100 mW), NO-OUTDOOR, DFS
(5470 - 5725 @ 40), (N/A, 500 mW), DFS
# Data from "Frequenznutzungsplan" (as published in April 2008), downloaded from
# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38448/publicationFile/2659/Frequenznutzungsplan2008_Id17448pdf.pdf
# For the 5GHz range also see
# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38216/publicationFile/6579/WLAN5GHzVfg7_2010_28042010pdf.pdf
# The values have been reduced by a factor of 2 (3db) for non TPC devices
# (in other words: devices with TPC can use twice the tx power of this table).
# Note that the docs do not require TPC for 5150--5250; the reduction to
# 100mW thus is not strictly required -- however the conservative 100mW
# limit is used here as the non-interference with radar and satellite
# apps relies on the attenuation by the building walls only in the
# absence of DFS; the neighbour countries have 100mW limit here as well.
country DE: DFS-ETSI
# entries 279004 and 280006
(2400 - 2483.5 @ 40), (N/A, 100 mW)
# entry 303005
(5150 - 5250 @ 40), (N/A, 100 mW), NO-OUTDOOR
# entries 304002 and 305002
(5250 - 5350 @ 40), (N/A, 100 mW), NO-OUTDOOR, DFS
# entries 308002, 309001 and 310003
(5470 - 5725 @ 40), (N/A, 500 mW), DFS
country DK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country DO:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country DZ:
(2402 - 2482 @ 40), (N/A, 20)
country EC:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country EE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country EG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country ES: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country FI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country FR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GE:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country GB: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GD:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country GR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country GL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
(5490 - 5710 @ 20), (N/A, 27), DFS
country GT:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country GU:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country HN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country HK:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country HR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country HT:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country HU: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country ID:
(2402 - 2482 @ 40), (N/A, 20)
country IE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country IL:
(2402 - 2482 @ 40), (N/A, 20)
(5150 - 5250 @ 40), (N/A, 200 mW), NO-OUTDOOR
(5250 - 5350 @ 40), (N/A, 200 mW), NO-OUTDOOR, DFS
country IN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country IS: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country IR:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country IT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country JM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country JP:
(2402 - 2472 @ 40), (N/A, 20)
(2457 - 2482 @ 20), (N/A, 20)
(2474 - 2494 @ 20), (N/A, 20), NO-OFDM
(4910 - 4930 @ 10), (N/A, 23)
(4910 - 4990 @ 40), (N/A, 23)
(4930 - 4950 @ 10), (N/A, 23)
(5030 - 5045 @ 10), (N/A, 23)
(5030 - 5090 @ 40), (N/A, 23)
(5050 - 5060 @ 10), (N/A, 23)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 23), DFS
country JO:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
country KE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country KH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country KP:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5330 @ 40), (3, 20)
(5160 - 5250 @ 40), (3, 20), DFS
(5490 - 5630 @ 40), (3, 30), DFS
(5735 - 5815 @ 40), (3, 30)
country KR:
(2402 - 2482 @ 20), (N/A, 20)
(5170 - 5250 @ 20), (3, 20)
(5250 - 5330 @ 20), (3, 20), DFS
(5490 - 5630 @ 20), (3, 30), DFS
(5735 - 5815 @ 20), (3, 30)
country KW:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
country KZ:
(2402 - 2482 @ 40), (N/A, 20)
country LB:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country LI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LK:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 20), DFS
(5490 - 5710 @ 20), (3, 20), DFS
(5735 - 5835 @ 20), (3, 30)
country LT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LU: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country LV: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MC: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 18)
(5250 - 5330 @ 40), (N/A, 18), DFS
country MA:
(2402 - 2482 @ 40), (N/A, 20)
country MO:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 23)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country MK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country MY:
(2402 - 2482 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 30), DFS
(5735 - 5835 @ 40), (N/A, 30)
country MX:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country NL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20), NO-OUTDOOR
(5250 - 5330 @ 40), (N/A, 20), NO-OUTDOOR, DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country NO: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country NP:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country NZ:
(2402 - 2482 @ 40), (N/A, 30)
(5170 - 5250 @ 20), (3, 23)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country OM:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country PA:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country PE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country PH:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PK:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country PL: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country PT: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country PR:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 23), DFS
(5735 - 5835 @ 40), (3, 30)
country QA:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country RO: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country RU:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 20), (N/A, 30)
country RW:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5835 @ 40), (N/A, 30)
country SA:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 23)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country SE: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SG:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5735 - 5835 @ 40), (N/A, 20)
country SI: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SK: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
(5490 - 5710 @ 40), (N/A, 27), DFS
country SV:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (3, 17)
(5250 - 5330 @ 20), (3, 23), DFS
(5735 - 5835 @ 20), (3, 30)
country SY:
(2402 - 2482 @ 40), (N/A, 20)
country TW:
(2402 - 2472 @ 40), (3, 27)
(5270 - 5330 @ 40), (3, 17), DFS
(5735 - 5815 @ 40), (3, 30)
country TH:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country TT:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country TN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country TR: DFS-ETSI
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 20), (N/A, 20)
(5250 - 5330 @ 20), (N/A, 20), DFS
country UA:
(2402 - 2482 @ 40), (N/A, 20)
country US: DFS-FCC
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5600 @ 40), (3, 20), DFS
(5650 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country UY:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country UZ:
(2402 - 2472 @ 40), (3, 27)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country VE:
(2402 - 2482 @ 40), (N/A, 20)
(5735 - 5815 @ 40), (N/A, 23)
country VN:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (N/A, 20)
(5250 - 5330 @ 40), (N/A, 20), DFS
country YE:
(2402 - 2482 @ 40), (N/A, 20)
country ZA:
(2402 - 2482 @ 40), (N/A, 20)
(5170 - 5250 @ 40), (3, 17)
(5250 - 5330 @ 40), (3, 20), DFS
(5490 - 5710 @ 40), (3, 20), DFS
(5735 - 5835 @ 40), (3, 30)
country ZW:
(2402 - 2482 @ 40), (N/A, 20)

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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-03-02T22:16:14+08:00
====== iw ======
Created Friday 02 March 2012
http://lists.gnu.org/archive/html/ltib/2009-10/msg00009.html
iw依赖于libnl，需要先安装libnl(__同时部署到目标板根文件系统中)__。
__一、LTIB安装方法：__
LTIB中加入iw支持的方法：
1.获得源代码 iw-3.3.tar.bz2 , 计算其md5值存入iw-3.3.tar.bz2.md5文件中。
#md5sumiw-3.3.tar.bz2 >iw-3.3.tar.bz2.md5
2.将源文件和md5值拷贝到/opt/freescale/pkgs
#cp iw* [[/opt/freescale/pkgs]]
3.向~/ppc/ltib-mpc8315/dist/lfs-5.1/中添加spec文件（可**以在template/template.spec的基础上修改**）
# cd [[~/ppc/ltib-mpc8315/dist/lfs-5.1]]
# mkdir iw
# cd iw
__# cat iw.spec__
%define pfx /opt/freescale/rootfs/%{_target_cpu}
Summary : iw
Name : iw
Version : 3.3
Release : 1
License : gpl
Vendor : Freescale
Packager : geekard
Group : Development/Tools
URL : http://uestc.edu.cn
Source : %{name}-%{version}.tar.bz2
BuildRoot : %{_tmppath}/%{name}
Prefix : %{pfx}
%Description
%{summary}
%Prep
%setup
%Build
#./configure --prefix=%{_prefix} --host=$CFGHOST --build=%{_build} __ #iw不需配置，直接编译__
make
%Install
rm -rf $RPM_BUILD_ROOT
make install DESTDIR=$RPM_BUILD_ROOT/%{pfx}
%Clean
rm -rf $RPM_BUILD_ROOT
%Files
%defattr(-,root,root)
%{pfx}/*
4. iw在编译的过程中需要生成version.c, 但是LTIB在编译过程中生成不了，提示错误。
version.c中的内容与体系结构无关，因此可以先在iw代码目录中运行make，将生成的version.c复制到ltib的目录中。
5. 配置，编译，安装
# cp [[/opt/freescale/pkgs/iw-3.3.tar.bz2]] [[/tmp]]
#cd [[/tmp;]] tar xvf iw-3.3.tar.bz2
# cd iw-3.3
#
#make #非交叉编译，这个过程中生成version.c
#cat version.c
#include "iw.h"
const char iw_version[] = "3.3-3-g135e65d";
#cd [[~/ppc/ltib-mpc8315/]]
#cp dist/lfs-1.5/iw/iw.spec .
#./ltib -m prep -p iw.spec #解压源代码到rpm/BUILD目录中
#cp [[/tmp/iw-3.3/version.c]] rpm/BUILD/iw-3.3 #将上一步生成的version.c复制到目录中
#./ltib -m scbuild -p iw.spec #编译
#./ltib -m scdeploy -p iw.spec #部署到根文件系统中
==== 二、使用交叉编译工具链的方法 ====
1.解压源代码：
$tar xvf iw-3.3.tar.bz2
$cd iw-3.3
2.在当前shell中导入交叉编译工具链的环境变量脚本：
$source [[~/PPC/script/env.h]]
3.交叉编译libnl
$CC=powerpc-e300c3-linux-gnu-gcc make
4. 安装到目标板的根文件系统中
$make DESTDIR=/path-to-target-root-dir install
iw.tar.bz2见attachment dir。

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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-03-02T22:05:51+08:00
====== libnl ======
Created Friday 02 March 2012
LTIB中加入libnl支持的方法：
==== 一、使用LTIB的方法： ====
1.下载libnl-3.2.11.tar.gz文件，计算其md5值。
#md5sum libnl-3.2.11.tar.gz >libnl-3.2.11.tar.gz.md5
2.将源文件和md5值拷贝到/opt/freescale/pkgs
#cp libnl* /opt/freescale/pkgs
3.向~/ppc/ltib-mpc8315/dist/lfs-5.1/中添加spec文件（可以在template/template.spec的基础上修改）
# cd ~/ppc/ltib-mpc8315/dist/lfs-5.1
# mkdir libnl
# cd libnl
__# cat libnl.spec__
%define pfx /opt/freescale/rootfs/%{_target_cpu}
Summary : libnl
Name : libnl
Version : 3.2.11
Release : 1 #任意值，必须要有。
License : gpl
Vendor : Freescale
Packager : geekard
Group : Development/Tools
URL : http://uestc.edu.cn
Source : __%{name}-%{version}.tar.gz #也可以手动指定全文件名，LTIB会到/opt/freescale/pkgs下查找该文件__
BuildRoot : %{_tmppath}/%{name}
Prefix : %{pfx}
%Description
%{summary}
%Prep
%setup
%Build
./configure --prefix=%{_prefix} --host=$CFGHOST --build=%{_build}
make
%Install
rm -rf $RPM_BUILD_ROOT
make install DESTDIR=$RPM_BUILD_ROOT/%{pfx}
%Clean
rm -rf $RPM_BUILD_ROOT
%Files
%defattr(-,root,root)
%{pfx}/*
4. 预处理，编译，部署(添加到根文件系统中)：
# cd ~/ppc/ltib-mpc8315
#cp dist/ltf-5.1/libnl/libnl.spec .
#./ltib -m prep -p libnl.spec
#./ltib -m scbuild -p libnl.spec
#./ltib -m scdeploy -p libnl.spec
== ==================== ==
-------------------------------------------------------------------------------
+ make
Making all in include
make[1]: Entering directory `/home/geekard/PPC/ltib-mpc8315erdb-20100719/rpm/BUILD/libnl-3.2.10/include'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/geekard/PPC/ltib-mpc8315erdb-20100719/rpm/BUILD/libnl-3.2.10/include'
Making all in lib
make[1]: Entering directory `/home/geekard/PPC/ltib-mpc8315erdb-20100719/rpm/BUILD/libnl-3.2.10/lib'
GEN route/pktloc_grammar.c
GEN route/cls/ematch_grammar.c
GEN route/cls/ematch_syntax.c
GEN route/pktloc_syntax.c
r__oute/cls/ematch_syntax.y:31.9-16: syntax error, unexpected identifier, expecting string__
make[1]: *** [route/cls/ematch_syntax.c] Error 1
make[1]: *** Waiting for unfinished jobs....
route/pktloc_syntax.y:11.9-16: syntax error, unexpected identifier, expecting string
make[1]: *** [route/pktloc_syntax.c] Error 1
make[1]: Leaving directory `/home/geekard/PPC/ltib-mpc8315erdb-20100719/rpm/BUILD/libnl-3.2.10/lib'
make: *** [all-recursive] Error 1
error: Bad exit status from /home/geekard/PPC/ltib-mpc8315erdb-20100719/tmp/rpm-tmp.19887 (%build)
原因是ltib使用的bison版本老了：
http://permalink.gmane.org/gmane.comp.lib.uclibc.buildroot/30794
----------------
commit: http://git.buildroot.net/buildroot/commit/?id=5c22f20f4b12395a34ce47c1aba608fccaf1fbe0
branch: http://git.buildroot.net/buildroot/commit/?id=refs/heads/master
libnl build breaks with bison <2.4 with:
bison -y -d -o route/cls/ematch_syntax.c route/cls/ematch_syntax.y
route/cls/ematch_syntax.y:31.9-16: syntax error, unexpected
identifier, expecting string
So build our own known good version and use instead.
-------------------
解决的方法是，将LTIB使用的bison指向系统较新的版本
# sudo ln -s /usr/bin/bison [[/opt/freescale/ltib/usr/bin/bison]]
-----------------------------------------------------------------------
> make[3]: Entering directory
> `/home/sriram/buildroot/buildroot-2011.11/output/build/libnl-3.0/lib'
> CC route/pktloc.lo
>
> route/pktloc.c: In function ‘read_pktlocs’:
> route/pktloc.c:127:34: error: __‘YY_BUF_SIZE’ undeclared__ (first use in
> this function)
> route/pktloc.c:127:34: note: each undeclared identifier is reported
> only once for each function it appears in
> make[3]: *** [route/pktloc.lo] Error 1
> make[3]: Leaving directory
> `/home/sriram/buildroot/buildroot-2011.11/output/build/libnl-3.0/lib'
> make[2]: *** [all] Error 2
> make[2]: Leaving directory
> `/home/sriram/buildroot/buildroot-2011.11/output/build/libnl-3.0/lib'
> make[1]: *** [all-recursive] Error 1
> make[1]: Leaving directory
> `/home/sriram/buildroot/buildroot-2011.11/output/build/libnl-3.0'
> make: ***
> [/home/sriram/buildroot/buildroot-2011.11/output/build/libnl-3.0/.stamp_built]
> Error 2
--------------------------------
解决方法是：http://lkml.indiana.edu/hypermail/linux/kernel/1202.2/01275.html
I added following lines of code in
libnl-3.0/lib/route/pktloc_grammer.h
#ifndef YY_BUF_SIZE
#define YY_BUF_SIZE 16384
#endif
#ifndef YY_STATE_BUF_SIZE
#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
#endif
==== 二、使用交叉编译工具链的方法 ====
1.解压源代码：
$tar xvf libnl-3.2.11.tar.gz
2.在当前shell中导入交叉编译工具链的环境变量脚本：
$source ~/PPC/script/env.h
3.交叉编译libnl
$ ./configure --prefix=/usr __--host=powerpc-linux --build=x86_64-unknown-linux-gnu #--build参数可以不用指定。__
$make
4. 安装到目标板的根文件系统中
$make install_root=/path-to-target-root-dir install
libnl-3.2.11文件件Attachment dir.

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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-08-03T21:05:12+08:00
====== ltib ======
Created Friday 03 August 2012
1. 安装rpm-org和cpio软件包
yoaurt -S rpm-org cpio
2. 改变/opt目录可写
sudo chmod -R 777 [[/opt]]
3. 安装：
perl-net-http和perl-lwp-protocol-https
4.执行/usr/sbin/visudo命令，在打开的文件中添加
geekard ALL = NOPASSWD: /bin/rpm, /opt/freescale/ltib/usr/bin/rpm
5.

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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-06-06T15:28:16+08:00
====== sparse ======
Created Wednesday 06 June 2012
parse.h:
struct /* labeled_struct */ {
struct symbol *label_identifier;
/* struct statement *label_statement; */ 注释掉这一个成员
};
然后在
[geekard@kb310 pkgs]$ tar -cvzf sparse-0.4.tar.gz sparse-0.4
[geekard@kb310 pkgs]$ md5sum sparse-0.4.tar.gz >sparse-0.4.tar.gz.md5
[geekard@kb310 pkgs]$
两文件位于附件中：
[[./sparse-0001.4.tar.gz]]
[[./sparse-0001.4.tar.gz.md5]]
[[./sparse-0001.4-array-fix.patch]]
[[./sparse-0001.4-array-fix.patch.md5]]

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Steve Papacharalambous <stevep@freescale.com> 20 September 2007
This patch fixes build errors when building with later versions of gcc due
to increased strictness when declaring array variables without a size:
[snip]
CC test-lexing.o
In file included from test-lexing.c:18:
token.h:59: array size missing in `name'
token.h:140: array size missing in `data'
make: *** [test-lexing.o] Error 1
[/snip]
diff -uNr sparse-0.4.orig/allocate.h sparse-0.4/allocate.h
--- sparse-0.4.orig/allocate.h Sat Sep 15 20:56:10 2007
+++ sparse-0.4/allocate.h Thu Sep 20 08:45:03 2007
@@ -4,7 +4,7 @@
struct allocation_blob {
struct allocation_blob *next;
unsigned int left, offset;
- unsigned char data[];
+ unsigned char *data;
};
struct allocator_struct {
diff -uNr sparse-0.4.orig/token.h sparse-0.4/token.h
--- sparse-0.4.orig/token.h Sat Sep 15 20:56:10 2007
+++ sparse-0.4/token.h Thu Sep 20 08:45:31 2007
@@ -56,7 +56,7 @@
unsigned char tainted:1,
reserved:1,
keyword:1;
- char name[]; /* Actual identifier */
+ char *name; /* Actual identifier */
};
enum token_type {
@@ -137,7 +137,7 @@
struct string {
unsigned int length;
- char data[];
+ char *data;
};
/* will fit into 32 bits */

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Steve Papacharalambous <stevep@freescale.com> 20 September 2007
This patch fixes build errors when building with later versions of gcc due
to increased strictness when declaring array variables without a size:
[snip]
CC test-lexing.o
In file included from test-lexing.c:18:
token.h:59: array size missing in `name'
token.h:140: array size missing in `data'
make: *** [test-lexing.o] Error 1
[/snip]
diff -uNr sparse-0.4.orig/allocate.h sparse-0.4/allocate.h
--- sparse-0.4.orig/allocate.h Sat Sep 15 20:56:10 2007
+++ sparse-0.4/allocate.h Thu Sep 20 08:45:03 2007
@@ -4,7 +4,7 @@
struct allocation_blob {
struct allocation_blob *next;
unsigned int left, offset;
- unsigned char data[];
+ unsigned char *data;
};
struct allocator_struct {
diff -uNr sparse-0.4.orig/token.h sparse-0.4/token.h
--- sparse-0.4.orig/token.h Sat Sep 15 20:56:10 2007
+++ sparse-0.4/token.h Thu Sep 20 08:45:31 2007
@@ -56,7 +56,7 @@
unsigned char tainted:1,
reserved:1,
keyword:1;
- char name[]; /* Actual identifier */
+ char *name; /* Actual identifier */
};
enum token_type {
@@ -137,7 +137,7 @@
struct string {
unsigned int length;
- char data[];
+ char *data;
};
/* will fit into 32 bits */

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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-08-02T15:31:27+08:00
====== uboot ======
Created Thursday 02 August 2012
1. ltib在编译uboot时长时间地停在下面的命令行上：
powerpc-e300c3-linux-gnu-objcopy -O srec u-boot u-boot.srec
powerpc-e300c3-linux-gnu-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
而且生成的uboot.bin文件非常大：
[geekard@kb310 ltib-mpc8315erdb-20100719]$ ls -lh rpm/BUILD/u-boot-2009.03-rc2/u-boot.bin
-rwxr-xr-x 1 geekard geekard 4.0G Aug 4 15:18 rpm/BUILD/u-boot-2009.03-rc2/u-boot.bin
[geekard@kb310 ltib-mpc8315erdb-20100719]$
-----------------------------------
用readelf探查显示结果如下：
[geekard@kb310 u-boot-2009.03-rc2]$ powerpc-e300c3-linux-gnu-readelf -l u-boot
Elf file type is EXEC (Executable file)
Entry point 0xfe000100
There are 3 program headers, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000094 __0x00000094__ 0x00000094 0x0b052 0x0b052 R 0x1
LOAD 0x00b0e8 0__xfe000000__ 0xfe000000 0x3f3ec 0x4877c RWE 0x8
GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RWE 0x4
Section to Segment mapping:
Segment Sections...
00 __.rodata.str1.1__
01 .text .text.unlikely .reloc .data .data.rel.ro.local .data.rel .data.rel.local .data.rel.ro .u_boot_cmd .bss
02
http://www.mail-archive.com/u-boot@lists.denx.de/msg06883.html
可见objcopy试图在u-boot.bin文件中的0x94到0xfe000000中填充0xff。解决方法是：
diff -purN orig/cpu/mpc83xx/u-boot.lds u-boot/cpu/mpc83xx/u-boot.lds
--- orig/cpu/mpc83xx/u-boot.lds 2008-12-29 14:26:05.000000000 -0500
+++ u-boot/cpu/mpc83xx/u-boot.lds 2008-12-29 14:26:13.000000000 -0500
@@ -57,6 +57,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
__+ *(.rodata.str1.1)__
*(.rodata.str1.4)
*(.eh_frame)
}
------------------
[geekard@kb310 ltib-mpc8315erdb-20100719]$ ./ltib -m prep -p u-boot
[geekard@kb310 ltib-mpc8315erdb-20100719]$ cp modify/uboot/__MPC8315ERDB.h__ rpm/BUILD/u-boot-2009.03-rc2/include/configs/
[geekard@kb310 ltib-mpc8315erdb-20100719]$ cp modify/uboot/__u-boot.lds__ rpm/BUILD/u-boot-2009.03-rc2/cpu/mpc83xx/
[geekard@kb310 ltib-mpc8315erdb-20100719]$ ./ltib -m scbuild -p u-boot
MPC8315ERDB.h文件修改DDR为512MB，关闭了eTSEC1.两文件位于附件中。
[[./MPC8315ERDB001.h]]
[[./u-boot001.lds]]

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/*
* Copyright (C) 2007, 2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* Jerry Huang <Chang-Ming.Huang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC831X 1 /* MPC831x CPU family */
#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#ifdef CONFIG_PCISLAVE
#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666667 /* in Hz */
#endif /* CONFIG_PCISLAVE */
/*
* The 8315 silicon has three speed grade, they are
* A: CORE/CSB = 400MHz/133MHz
* B: CORE/CSB = 333MHz/133MHz
* C: CORE/CSB = 266MHz/133MHz
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
* We choose the A type silicon as default, so the core is 400Mhz.
*/
#define CONFIG_SYS_FREQ_400MHz 1
#define CONFIG_SYS_FREQ_333MHz 2
#define CONFIG_SYS_FREQ_266MHz 3
#ifndef CONFIG_CORE_FREQ
#define CONFIG_CORE_FREQ CONFIG_SYS_FREQ_400MHz
#endif
#if (CONFIG_CORE_FREQ == CONFIG_SYS_FREQ_266MHz)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1)
#elif (CONFIG_CORE_FREQ == CONFIG_SYS_FREQ_333MHz)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2_5X1)
#else
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_3X1)
#endif
#ifdef CONFIG_NAND_SPL
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#endif
#else
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#endif
#endif
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Arbiter Setup
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
| DDRCDR_PZ_LOZ \
| DDRCDR_NZ_LOZ \
| DDRCDR_ODT \
| DDRCDR_Q_DRN )
/* 0x7b880001 */
/*
* Manually set up DDR parameters
* consist of two chips HY5PS12621BFP-C4 from HYNIX
*/
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
| ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
| ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00140000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_SYS_FLASH_BR_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
| BR_V ) /* valid */
#define CONFIG_SYS_FLASH_OR_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
| OR_GPCM_EAD )
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
/*
* NAND Flash on the Local Bus
*/
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#ifndef CONFIG_NAND_ECC_OFF
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
#else
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V )
#endif
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR )
/* 0xFFFF8396 */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
/*
* Swap CS0 / CS1 based upon NAND or NOR Flash Boot mode
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif /* CONFIG_NAND_U_BOOT */
/*
* NAND Boot Configuration, for board/../nand_boot.c
*/
#define CONFIG_SYS_NAND_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_NAND_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_NAND_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
#undef CONFIG_SYS_NAND_BOOT_QUIET /* Enable NAND boot status messages */
#define CONFIG_SYS_NAND_BOOT_SHOW_ECC_NUM /* Show corrected ECC errors */
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS (5) /* Bad block marker location */
#define CONFIG_SYS_NAND_FMR ((15 << FMR_CWTO_SHIFT) | (0 << FMR_AL_SHIFT))
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000) /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_NAND_U_BOOT_DST + 0x120) /* NUB start */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10)
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
/*
* JFFS2 configuration
*/
#define CONFIG_JFFS2_NAND
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=nor,nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:-@4m(jffs2)"
#define NAND_CACHE_PAGES 32
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK gd->csb_clk
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* Board info - revision and where boot from
*/
#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
#define CONFIG_83XX_GENERIC_PCIE 1
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
#define PCI_VENDOR_ID_FREESCALE 0x1957
#define PCI_DEVICE_ID_MPC8315E 0x00b4
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_SKIP_PCI_SCAN
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_HAS_FSL_DR_USB
/*
* TSEC
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/*
* TSEC ethernet configuration
*/
#define CONFIG_MII 1 /* MII PHY management */
//#define CONFIG_TSEC1 1
//#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC0"
//#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
//#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
//#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
/*
* SATA
*/
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif
/*
* Environment
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((1024<<10) - (CONFIG_SYS_NAND_BLOCK_SIZE<<1))
#elif !defined(CFG_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_FDT
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable, low 256MB */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* DDR: cache cacheable, high 256MB */
#define CONFIG_SYS_IBAT6L (0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 04:00:00:00:00:0A
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 04:00:00:00:00:0B
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8315erdb.dtb\0" \
"pciconfighost=yes\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

756
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@@ -0,0 +1,756 @@
/*
* Copyright (C) 2007, 2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* Jerry Huang <Chang-Ming.Huang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC831X 1 /* MPC831x CPU family */
#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#ifdef CONFIG_PCISLAVE
#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666667 /* in Hz */
#endif /* CONFIG_PCISLAVE */
/*
* The 8315 silicon has three speed grade, they are
* A: CORE/CSB = 400MHz/133MHz
* B: CORE/CSB = 333MHz/133MHz
* C: CORE/CSB = 266MHz/133MHz
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
* We choose the A type silicon as default, so the core is 400Mhz.
*/
#define CONFIG_SYS_FREQ_400MHz 1
#define CONFIG_SYS_FREQ_333MHz 2
#define CONFIG_SYS_FREQ_266MHz 3
#ifndef CONFIG_CORE_FREQ
#define CONFIG_CORE_FREQ CONFIG_SYS_FREQ_400MHz
#endif
#if (CONFIG_CORE_FREQ == CONFIG_SYS_FREQ_266MHz)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1)
#elif (CONFIG_CORE_FREQ == CONFIG_SYS_FREQ_333MHz)
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2_5X1)
#else
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_3X1)
#endif
#ifdef CONFIG_NAND_SPL
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#endif
#else
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#endif
#endif
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Arbiter Setup
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
| DDRCDR_PZ_LOZ \
| DDRCDR_NZ_LOZ \
| DDRCDR_ODT \
| DDRCDR_Q_DRN )
/* 0x7b880001 */
/*
* Manually set up DDR parameters
* consist of two chips HY5PS12621BFP-C4 from HYNIX
*/
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
| ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
| ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00140000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_SYS_FLASH_BR_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
| BR_V ) /* valid */
#define CONFIG_SYS_FLASH_OR_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
| OR_GPCM_EAD )
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
/*
* NAND Flash on the Local Bus
*/
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#ifndef CONFIG_NAND_ECC_OFF
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
#else
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V )
#endif
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR )
/* 0xFFFF8396 */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
/*
* Swap CS0 / CS1 based upon NAND or NOR Flash Boot mode
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif /* CONFIG_NAND_U_BOOT */
/*
* NAND Boot Configuration, for board/../nand_boot.c
*/
#define CONFIG_SYS_NAND_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_NAND_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_NAND_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
#undef CONFIG_SYS_NAND_BOOT_QUIET /* Enable NAND boot status messages */
#define CONFIG_SYS_NAND_BOOT_SHOW_ECC_NUM /* Show corrected ECC errors */
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS (5) /* Bad block marker location */
#define CONFIG_SYS_NAND_FMR ((15 << FMR_CWTO_SHIFT) | (0 << FMR_AL_SHIFT))
#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_DST (0x01000000) /* Load NUB to this addr */
#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_NAND_U_BOOT_DST + 0x120) /* NUB start */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10)
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
/*
* JFFS2 configuration
*/
#define CONFIG_JFFS2_NAND
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=nor,nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:-@4m(jffs2)"
#define NAND_CACHE_PAGES 32
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK gd->csb_clk
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* Board info - revision and where boot from
*/
#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE 0x00000000
#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
#define CONFIG_83XX_GENERIC_PCIE 1
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
#define PCI_VENDOR_ID_FREESCALE 0x1957
#define PCI_DEVICE_ID_MPC8315E 0x00b4
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_SKIP_PCI_SCAN
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_HAS_FSL_DR_USB
/*
* TSEC
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/*
* TSEC ethernet configuration
*/
#define CONFIG_MII 1 /* MII PHY management */
//#define CONFIG_TSEC1 1
//#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC0"
//#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
//#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
//#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
/*
* SATA
*/
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET 0x18000
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET 0x19000
#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif
/*
* Environment
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((1024<<10) - (CONFIG_SYS_NAND_BLOCK_SIZE<<1))
#elif !defined(CFG_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_FDT
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable, low 256MB */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
/* DDR: cache cacheable, high 256MB */
#define CONFIG_SYS_IBAT6L (0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 04:00:00:00:00:0A
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 04:00:00:00:00:0B
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8315erdb.dtb\0" \
"pciconfighost=yes\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc83xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

125
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/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc83xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

21
Zim/Research/Error_Notes/编译错误/udev.txt Normal file
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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-08-04T20:47:40+08:00
====== udev ======
Created Saturday 04 August 2012
编译时出现下列错误：
udevd.c: In function 'udev_event_run':
udevd.c:239:3: warning: implicit declaration of function 'setpriority' [-Wimplicit-function-declaration]
udevd.c:239:3: warning: nested extern declaration of 'setpriority' [-Wnested-externs]
udevd.c:239:15: error: 'PRIO_PROCESS' undeclared (first use in this function)
udevd.c:239:15: note: each undeclared identifier is reported only once for each function it appears in
udevd.c: In function 'main':
udevd.c:1085:14: error: 'PRIO_PROCESS' undeclared (first use in this function)
-----------------
解决方法是：
在udevd.c中加入：
#define PRIO_PROCESS 0
即可

8
Zim/Research/Error_Notes/编译错误/不要安装nfs-utils和portmap以及modinits软件包.txt Normal file
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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-02-22T11:06:09+08:00
====== 不要安装nfs-utils和portmap以及modinits软件包 ======
Created Wednesday 22 February 2012
由于busybox没有安装nfs工具包(目前还没解决)，所以在ltib的package list中不要选择上面的三个软件包。

19
Zim/Research/Error_Notes/编译错误/编译glibc和base_libs提示不兼容的libc.so.txt Normal file
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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-02-22T10:35:27+08:00
====== 编译glibc和base libs提示不兼容的libc.so ======
Created Wednesday 22 February 2012
http://www.mail-archive.com/ltib@nongnu.org/msg00623.html
这是由于glibc和base_libs的rpm控制脚本存在bug。
修改ltib目录下的dist/lfs-xx/glibc|base_libs目录下的spec文件中下面部分：
# remove absolute paths from text search files (if they exist)
perl -w -e '
- @ARGV = grep { `file $_` =~ m,ASCII C program text, } @ARGV;
+ @ARGV = grep { `file $_` =~ m,ASCII\s+.*text, } @ARGV;
RTW：这其实是__将生成的libc.so和libc_noshared.so中的绝对路径去掉__。
在新版本的工具链制作脚本中已经自动打上了上面的patch。

17
Zim/Research/Error_Notes/编译错误/编译新内核(3.1.8)是出现没找到mpc8315erdb-default.dts错误.txt Normal file
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Content-Type: text/x-zim-wiki
Wiki-Format: zim 0.4
Creation-Date: 2012-02-21T16:12:49+08:00
====== 编译新内核(3.1.8)是出现没找到mpc8315erdb-default.dts错误 ======
Created Tuesday 21 February 2012
原因是新内核目录arch/powerpc/boot/dts/目录下的没有mpc8315erdb*系列文件，可以将ISO中的老内核(位于/opt/freescale/pkgs/linux-2.29.6.tar.bz2)同一目录下的mpc8315**系列文件拷贝到新内核目录。
[[./mpc8315erdb-1588.dts]]
[[./mpc8315erdb-default.dts]]
[[./mpc8315erdb-otg.dts]]
[[./mpc8315erdb-ulpi.dts]]
[[./mpc8315erdb.dts]]

464
Zim/Research/Error_Notes/编译错误/编译新内核(3.1.8)是出现没找到mpc8315erdb-default.dts错误/mpc8315erdb-1588.dts Normal file
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/dts-v1/;
/ {
compatible = "fsl,mpc8315erdb";
#address-cells = <0x1>;
#size-cells = <0x1>;
aliases {
ethernet0 = "/immr@e0000000/ethernet@24000";
ethernet1 = "/immr@e0000000/ethernet@25000";
serial0 = "/immr@e0000000/serial@4500";
serial1 = "/immr@e0000000/serial@4600";
pci0 = "/pci@e0008500";
pcie0 = "/pci@e0009000";
pcie1 = "/pci@e000a000";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
PowerPC,8315@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <0x20>;
i-cache-line-size = <0x20>;
d-cache-size = <0x4000>;
i-cache-size = <0x4000>;
timebase-frequency = <0x0>;
bus-frequency = <0x0>;
clock-frequency = <0x0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x8000000>;
};
localbus@e0005000 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <0x4d 0x8>;
interrupt-parent = <0x1>;
ranges = <0x0 0x0 0xfe000000 0x800000 0x1 0x0 0xe0600000 0x2000 0x2 0x0 0xf0000000 0x20000 0x3 0x0 0xfa000000 0x8000>;
flash@0,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <0x2>;
device-width = <0x1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x400000>;
};
kernel@500000 {
reg = <0x500000 0x200000>;
};
dtb@700000 {
reg = <0x700000 0x100000>;
};
};
nand@1,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-fcm-nand", "fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
label = "U-Boot-NAND";
};
jffs2@100000 {
reg = <0x100000 0x800000>;
label = "JFFS2-NAND";
};
ramdisk@900000 {
reg = <0x900000 0x400000>;
label = "Ramdisk-NAND";
};
reserved@d00000 {
reg = <0xd00000 0x1000000>;
label = "Reserved-NAND";
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
read-only;
label = "Kernel-NAND";
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
read-only;
label = "DTB-NAND";
};
};
};
immr@e0000000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x200>;
bus-frequency = <0x0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <0x0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0xe 0x8>;
interrupt-parent = <0x1>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
mcu@a {
#gpio-cells = <0x2>;
compatible = "fsl,mc9s08qg8-mpc8315erdb", "fsl,mcu-mpc8349emitx";
reg = <0xa>;
gpio-controller;
};
};
spi@7000 {
cell-index = <0x0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = <0x1>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
reg = <0x82a8 0x4>;
ranges = <0x0 0x8100 0x1a8>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
cell-index = <0x0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x0 0x80>;
cell-index = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <0x1>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <0x3>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x26 0x8>;
phy_type = "utmi";
sleep = <0x2 0xc00000>;
};
mdio@24520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
interrupt-parent = <0x1>;
interrupts = <0x14 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
linux,phandle = <0x4>;
};
ethernet-phy@1 {
interrupt-parent = <0x1>;
interrupts = <0x13 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
linux,phandle = <0x7>;
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x3>;
};
};
mdio@25520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x6>;
};
};
ptimer@24e00 {
compatible = "fsl,gianfar-ptp-timer";
reg = <0x24e00 0xb0>;
linux,phandle = <0x5>;
};
ethernet@24000 {
cell-index = <0x0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x3>;
phy-handle = <0x4>;
sleep = <0x2 0xc0000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
ethernet@25000 {
cell-index = <0x1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x6>;
phy-handle = <0x7>;
sleep = <0x2 0x30000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
serial@4500 {
cell-index = <0x0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0x9 0x8>;
interrupt-parent = <0x1>;
};
serial@4600 {
cell-index = <0x1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0xa 0x8>;
interrupt-parent = <0x1>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <0xb 0x8>;
interrupt-parent = <0x1>;
fsl,num-channels = <0x4>;
fsl,channel-fifo-len = <0x18>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3ab0abf>;
};
sata@18000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <0x1>;
interrupts = <0x2c 0x8>;
interrupt-parent = <0x1>;
};
sata@19000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <0x2>;
interrupts = <0x2d 0x8>;
interrupt-parent = <0x1>;
};
tdm@16000 {
device_type = "tdm";
compatible = "fsl,mpc8315-tdm";
reg = <0x16000 0x200 0x2c000 0x2000>;
clock-frequency = <0x0>;
interrupts = <0x53 0x8 0x5e 0x8 0x3 0x8>;
interrupt-parent = <0x1>;
};
legerity {
device_type = "slic";
compatible = "legerity-slic";
clock-frequency = <0x0>;
interrupts = <0x16 0x8>;
interrupt-parent = <0x1>;
};
gpio@c00 {
device_type = "gpio";
compatible = "fsl,mpc8315-gpio";
reg = <0xc00 0x18>;
interrupt-parent = <0x1>;
};
interrupt-controller@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x2>;
reg = <0x700 0x100>;
device_type = "ipic";
linux,phandle = <0x1>;
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0x0 0x100>;
interrupts = <0x43 0x8 0x4 0x8 0x51 0x8 0x52 0x8 0x56 0x8 0x57 0x8 0x58 0x8 0x59 0x8>;
interrupt-parent = <0x1>;
};
power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <0x50 0x8>;
interrupt-parent = <0x1>;
fsl,mpc8313-wakeup-timer = <0x8>;
linux,phandle = <0x2>;
};
timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5a 0x8 0x4e 0x8 0x54 0x8 0x48 0x8>;
interrupt-parent = <0x1>;
linux,phandle = <0x8>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5b 0x8 0x4f 0x8 0x55 0x8 0x49 0x8>;
interrupt-parent = <0x1>;
};
};
pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <0x7000 0x0 0x0 0x1 0x1 0x12 0x8 0x7000 0x0 0x0 0x2 0x1 0x12 0x8 0x7000 0x0 0x0 0x3 0x1 0x12 0x8 0x7000 0x0 0x0 0x4 0x1 0x12 0x8 0x7800 0x0 0x0 0x1 0x1 0x11 0x8 0x7800 0x0 0x0 0x2 0x1 0x11 0x8 0x7800 0x0 0x0 0x3 0x1 0x11 0x8 0x7800 0x0 0x0 0x4 0x1 0x11 0x8 0x8000 0x0 0x0 0x1 0x1 0x30 0x8 0x8000 0x0 0x0 0x2 0x1 0x11 0x8 0x8000 0x0 0x0 0x3 0x1 0x30 0x8 0x8000 0x0 0x0 0x4 0x1 0x11 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x42 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x1000000 0x0 0x0 0xe0300000 0x0 0x100000>;
clock-frequency = <0x3f940aa>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0008500 0x100 0xe0008300 0x8>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0009000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x1 0x8 0x0 0x0 0x0 0x2 0x1 0x1 0x8 0x0 0x0 0x0 0x3 0x1 0x1 0x8 0x0 0x0 0x0 0x4 0x1 0x1 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x1 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xb1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0009000 0x1000 0xb0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
pci@e000a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x2 0x8 0x0 0x0 0x0 0x2 0x1 0x2 0x8 0x0 0x0 0x0 0x3 0x1 0x2 0x8 0x0 0x0 0x0 0x4 0x1 0x2 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x2 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xd1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe000a000 0x1000 0xd0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
};

456
Zim/Research/Error_Notes/编译错误/编译新内核(3.1.8)是出现没找到mpc8315erdb-default.dts错误/mpc8315erdb-default.dts Normal file
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/dts-v1/;
/ {
compatible = "fsl,mpc8315erdb";
#address-cells = <0x1>;
#size-cells = <0x1>;
aliases {
ethernet0 = "/immr@e0000000/ethernet@24000";
ethernet1 = "/immr@e0000000/ethernet@25000";
serial0 = "/immr@e0000000/serial@4500";
serial1 = "/immr@e0000000/serial@4600";
pci0 = "/pci@e0008500";
pcie0 = "/pci@e0009000";
pcie1 = "/pci@e000a000";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
PowerPC,8315@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <0x20>;
i-cache-line-size = <0x20>;
d-cache-size = <0x4000>;
i-cache-size = <0x4000>;
timebase-frequency = <0x0>;
bus-frequency = <0x0>;
clock-frequency = <0x0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x8000000>;
};
localbus@e0005000 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <0x4d 0x8>;
interrupt-parent = <0x1>;
ranges = <0x0 0x0 0xfe000000 0x800000 0x1 0x0 0xe0600000 0x2000 0x2 0x0 0xf0000000 0x20000 0x3 0x0 0xfa000000 0x8000>;
flash@0,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <0x2>;
device-width = <0x1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x400000>;
};
kernel@500000 {
reg = <0x500000 0x200000>;
};
dtb@700000 {
reg = <0x700000 0x100000>;
};
};
nand@1,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-fcm-nand", "fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
label = "U-Boot-NAND";
};
jffs2@100000 {
reg = <0x100000 0x800000>;
label = "JFFS2-NAND";
};
ramdisk@900000 {
reg = <0x900000 0x400000>;
label = "Ramdisk-NAND";
};
reserved@d00000 {
reg = <0xd00000 0x1000000>;
label = "Reserved-NAND";
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
read-only;
label = "Kernel-NAND";
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
read-only;
label = "DTB-NAND";
};
};
};
immr@e0000000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x200>;
bus-frequency = <0x0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <0x0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0xe 0x8>;
interrupt-parent = <0x1>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
mcu@a {
#gpio-cells = <0x2>;
compatible = "fsl,mc9s08qg8-mpc8315erdb", "fsl,mcu-mpc8349emitx";
reg = <0xa>;
gpio-controller;
};
};
spi@7000 {
cell-index = <0x0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = <0x1>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
reg = <0x82a8 0x4>;
ranges = <0x0 0x8100 0x1a8>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
cell-index = <0x0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x0 0x80>;
cell-index = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <0x1>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <0x3>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x26 0x8>;
phy_type = "utmi";
sleep = <0x2 0xc00000>;
};
mdio@24520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
interrupt-parent = <0x1>;
interrupts = <0x14 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
linux,phandle = <0x4>;
};
ethernet-phy@1 {
interrupt-parent = <0x1>;
interrupts = <0x13 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
linux,phandle = <0x6>;
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x3>;
};
};
mdio@25520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x5>;
};
};
ethernet@24000 {
cell-index = <0x0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x3>;
phy-handle = <0x4>;
sleep = <0x2 0xc0000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
};
ethernet@25000 {
cell-index = <0x1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x5>;
phy-handle = <0x6>;
sleep = <0x2 0x30000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
};
serial@4500 {
cell-index = <0x0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0x9 0x8>;
interrupt-parent = <0x1>;
};
serial@4600 {
cell-index = <0x1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0xa 0x8>;
interrupt-parent = <0x1>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <0xb 0x8>;
interrupt-parent = <0x1>;
fsl,num-channels = <0x4>;
fsl,channel-fifo-len = <0x18>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3ab0abf>;
};
sata@18000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <0x1>;
interrupts = <0x2c 0x8>;
interrupt-parent = <0x1>;
};
sata@19000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <0x2>;
interrupts = <0x2d 0x8>;
interrupt-parent = <0x1>;
};
tdm@16000 {
device_type = "tdm";
compatible = "fsl,mpc8315-tdm";
reg = <0x16000 0x200 0x2c000 0x2000>;
clock-frequency = <0x0>;
interrupts = <0x53 0x8 0x5e 0x8 0x3 0x8>;
interrupt-parent = <0x1>;
};
legerity {
device_type = "slic";
compatible = "legerity-slic";
clock-frequency = <0x0>;
interrupts = <0x16 0x8>;
interrupt-parent = <0x1>;
};
gpio@c00 {
device_type = "gpio";
compatible = "fsl,mpc8315-gpio";
reg = <0xc00 0x18>;
interrupt-parent = <0x1>;
};
interrupt-controller@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x2>;
reg = <0x700 0x100>;
device_type = "ipic";
linux,phandle = <0x1>;
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0x0 0x100>;
interrupts = <0x43 0x8 0x4 0x8 0x51 0x8 0x52 0x8 0x56 0x8 0x57 0x8 0x58 0x8 0x59 0x8>;
interrupt-parent = <0x1>;
};
power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <0x50 0x8>;
interrupt-parent = <0x1>;
fsl,mpc8313-wakeup-timer = <0x7>;
linux,phandle = <0x2>;
};
timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5a 0x8 0x4e 0x8 0x54 0x8 0x48 0x8>;
interrupt-parent = <0x1>;
linux,phandle = <0x7>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5b 0x8 0x4f 0x8 0x55 0x8 0x49 0x8>;
interrupt-parent = <0x1>;
};
};
pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <0x7000 0x0 0x0 0x1 0x1 0x12 0x8 0x7000 0x0 0x0 0x2 0x1 0x12 0x8 0x7000 0x0 0x0 0x3 0x1 0x12 0x8 0x7000 0x0 0x0 0x4 0x1 0x12 0x8 0x7800 0x0 0x0 0x1 0x1 0x11 0x8 0x7800 0x0 0x0 0x2 0x1 0x11 0x8 0x7800 0x0 0x0 0x3 0x1 0x11 0x8 0x7800 0x0 0x0 0x4 0x1 0x11 0x8 0x8000 0x0 0x0 0x1 0x1 0x30 0x8 0x8000 0x0 0x0 0x2 0x1 0x11 0x8 0x8000 0x0 0x0 0x3 0x1 0x30 0x8 0x8000 0x0 0x0 0x4 0x1 0x11 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x42 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x1000000 0x0 0x0 0xe0300000 0x0 0x100000>;
clock-frequency = <0x3f940aa>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0008500 0x100 0xe0008300 0x8>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0009000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x1 0x8 0x0 0x0 0x0 0x2 0x1 0x1 0x8 0x0 0x0 0x0 0x3 0x1 0x1 0x8 0x0 0x0 0x0 0x4 0x1 0x1 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x1 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xb1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0009000 0x1000 0xb0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
pci@e000a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x2 0x8 0x0 0x0 0x0 0x2 0x1 0x2 0x8 0x0 0x0 0x0 0x3 0x1 0x2 0x8 0x0 0x0 0x0 0x4 0x1 0x2 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x2 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xd1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe000a000 0x1000 0xd0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
};

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/dts-v1/;
/ {
compatible = "fsl,mpc8315erdb";
#address-cells = <0x1>;
#size-cells = <0x1>;
aliases {
ethernet0 = "/immr@e0000000/ethernet@24000";
ethernet1 = "/immr@e0000000/ethernet@25000";
serial0 = "/immr@e0000000/serial@4500";
serial1 = "/immr@e0000000/serial@4600";
pci0 = "/pci@e0008500";
pcie0 = "/pci@e0009000";
pcie1 = "/pci@e000a000";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
PowerPC,8315@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <0x20>;
i-cache-line-size = <0x20>;
d-cache-size = <0x4000>;
i-cache-size = <0x4000>;
timebase-frequency = <0x0>;
bus-frequency = <0x0>;
clock-frequency = <0x0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x8000000>;
};
localbus@e0005000 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <0x4d 0x8>;
interrupt-parent = <0x1>;
ranges = <0x0 0x0 0xfe000000 0x800000 0x1 0x0 0xe0600000 0x2000 0x2 0x0 0xf0000000 0x20000 0x3 0x0 0xfa000000 0x8000>;
flash@0,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <0x2>;
device-width = <0x1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x400000>;
};
kernel@500000 {
reg = <0x500000 0x200000>;
};
dtb@700000 {
reg = <0x700000 0x100000>;
};
};
nand@1,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-fcm-nand", "fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
label = "U-Boot-NAND";
};
jffs2@100000 {
reg = <0x100000 0x800000>;
label = "JFFS2-NAND";
};
ramdisk@900000 {
reg = <0x900000 0x400000>;
label = "Ramdisk-NAND";
};
reserved@d00000 {
reg = <0xd00000 0x1000000>;
label = "Reserved-NAND";
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
read-only;
label = "Kernel-NAND";
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
read-only;
label = "DTB-NAND";
};
};
};
immr@e0000000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x200>;
bus-frequency = <0x0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <0x0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0xe 0x8>;
interrupt-parent = <0x1>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
mcu@a {
#gpio-cells = <0x2>;
compatible = "fsl,mc9s08qg8-mpc8315erdb", "fsl,mcu-mpc8349emitx";
reg = <0xa>;
gpio-controller;
};
};
spi@7000 {
cell-index = <0x0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = <0x1>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
reg = <0x82a8 0x4>;
ranges = <0x0 0x8100 0x1a8>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
cell-index = <0x0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x0 0x80>;
cell-index = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <0x1>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <0x3>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x26 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
sleep = <0x2 0xc00000>;
};
mdio@24520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
interrupt-parent = <0x1>;
interrupts = <0x14 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
linux,phandle = <0x4>;
};
ethernet-phy@1 {
interrupt-parent = <0x1>;
interrupts = <0x13 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
linux,phandle = <0x7>;
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x3>;
};
};
mdio@25520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x6>;
};
};
ptimer@24e00 {
compatible = "fsl,gianfar-ptp-timer";
reg = <0x24e00 0xb0>;
linux,phandle = <0x5>;
};
ethernet@24000 {
cell-index = <0x0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x3>;
phy-handle = <0x4>;
sleep = <0x2 0xc0000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
ethernet@25000 {
cell-index = <0x1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x6>;
phy-handle = <0x7>;
sleep = <0x2 0x30000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
serial@4500 {
cell-index = <0x0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0x9 0x8>;
interrupt-parent = <0x1>;
};
serial@4600 {
cell-index = <0x1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0xa 0x8>;
interrupt-parent = <0x1>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <0xb 0x8>;
interrupt-parent = <0x1>;
fsl,num-channels = <0x4>;
fsl,channel-fifo-len = <0x18>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3ab0abf>;
};
sata@18000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <0x1>;
interrupts = <0x2c 0x8>;
interrupt-parent = <0x1>;
};
sata@19000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <0x2>;
interrupts = <0x2d 0x8>;
interrupt-parent = <0x1>;
};
tdm@16000 {
device_type = "tdm";
compatible = "fsl,mpc8315-tdm";
reg = <0x16000 0x200 0x2c000 0x2000>;
clock-frequency = <0x0>;
interrupts = <0x53 0x8 0x5e 0x8 0x3 0x8>;
interrupt-parent = <0x1>;
};
legerity {
device_type = "slic";
compatible = "legerity-slic";
clock-frequency = <0x0>;
interrupts = <0x16 0x8>;
interrupt-parent = <0x1>;
};
gpio@c00 {
device_type = "gpio";
compatible = "fsl,mpc8315-gpio";
reg = <0xc00 0x18>;
interrupt-parent = <0x1>;
};
interrupt-controller@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x2>;
reg = <0x700 0x100>;
device_type = "ipic";
linux,phandle = <0x1>;
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0x0 0x100>;
interrupts = <0x43 0x8 0x4 0x8 0x51 0x8 0x52 0x8 0x56 0x8 0x57 0x8 0x58 0x8 0x59 0x8>;
interrupt-parent = <0x1>;
};
power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <0x50 0x8>;
interrupt-parent = <0x1>;
fsl,mpc8313-wakeup-timer = <0x8>;
linux,phandle = <0x2>;
};
timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5a 0x8 0x4e 0x8 0x54 0x8 0x48 0x8>;
interrupt-parent = <0x1>;
linux,phandle = <0x8>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5b 0x8 0x4f 0x8 0x55 0x8 0x49 0x8>;
interrupt-parent = <0x1>;
};
};
pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <0x7000 0x0 0x0 0x1 0x1 0x12 0x8 0x7000 0x0 0x0 0x2 0x1 0x12 0x8 0x7000 0x0 0x0 0x3 0x1 0x12 0x8 0x7000 0x0 0x0 0x4 0x1 0x12 0x8 0x7800 0x0 0x0 0x1 0x1 0x11 0x8 0x7800 0x0 0x0 0x2 0x1 0x11 0x8 0x7800 0x0 0x0 0x3 0x1 0x11 0x8 0x7800 0x0 0x0 0x4 0x1 0x11 0x8 0x8000 0x0 0x0 0x1 0x1 0x30 0x8 0x8000 0x0 0x0 0x2 0x1 0x11 0x8 0x8000 0x0 0x0 0x3 0x1 0x30 0x8 0x8000 0x0 0x0 0x4 0x1 0x11 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x42 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x1000000 0x0 0x0 0xe0300000 0x0 0x100000>;
clock-frequency = <0x3f940aa>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0008500 0x100 0xe0008300 0x8>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0009000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x1 0x8 0x0 0x0 0x0 0x2 0x1 0x1 0x8 0x0 0x0 0x0 0x3 0x1 0x1 0x8 0x0 0x0 0x0 0x4 0x1 0x1 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x1 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xb1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0009000 0x1000 0xb0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
pci@e000a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x2 0x8 0x0 0x0 0x0 0x2 0x1 0x2 0x8 0x0 0x0 0x0 0x3 0x1 0x2 0x8 0x0 0x0 0x0 0x4 0x1 0x2 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x2 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xd1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe000a000 0x1000 0xd0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
};

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/dts-v1/;
/ {
compatible = "fsl,mpc8315erdb";
#address-cells = <0x1>;
#size-cells = <0x1>;
aliases {
ethernet0 = "/immr@e0000000/ethernet@24000";
ethernet1 = "/immr@e0000000/ethernet@25000";
serial0 = "/immr@e0000000/serial@4500";
serial1 = "/immr@e0000000/serial@4600";
pci0 = "/pci@e0008500";
pcie0 = "/pci@e0009000";
pcie1 = "/pci@e000a000";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
PowerPC,8315@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <0x20>;
i-cache-line-size = <0x20>;
d-cache-size = <0x4000>;
i-cache-size = <0x4000>;
timebase-frequency = <0x0>;
bus-frequency = <0x0>;
clock-frequency = <0x0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x8000000>;
};
localbus@e0005000 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <0x4d 0x8>;
interrupt-parent = <0x1>;
ranges = <0x0 0x0 0xfe000000 0x800000 0x1 0x0 0xe0600000 0x2000 0x2 0x0 0xf0000000 0x20000 0x3 0x0 0xfa000000 0x8000>;
flash@0,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <0x2>;
device-width = <0x1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x400000>;
};
kernel@500000 {
reg = <0x500000 0x200000>;
};
dtb@700000 {
reg = <0x700000 0x100000>;
};
};
nand@1,0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-fcm-nand", "fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
label = "U-Boot-NAND";
};
jffs2@100000 {
reg = <0x100000 0x800000>;
label = "JFFS2-NAND";
};
ramdisk@900000 {
reg = <0x900000 0x400000>;
label = "Ramdisk-NAND";
};
reserved@d00000 {
reg = <0xd00000 0x1000000>;
label = "Reserved-NAND";
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
read-only;
label = "Kernel-NAND";
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
read-only;
label = "DTB-NAND";
};
};
};
immr@e0000000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x200>;
bus-frequency = <0x0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <0x0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0xe 0x8>;
interrupt-parent = <0x1>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
mcu@a {
#gpio-cells = <0x2>;
compatible = "fsl,mc9s08qg8-mpc8315erdb", "fsl,mcu-mpc8349emitx";
reg = <0xa>;
gpio-controller;
};
};
spi@7000 {
cell-index = <0x0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <0x10 0x8>;
interrupt-parent = <0x1>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
reg = <0x82a8 0x4>;
ranges = <0x0 0x8100 0x1a8>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
cell-index = <0x0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x0 0x80>;
cell-index = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <0x1>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <0x2>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <0x3>;
interrupt-parent = <0x1>;
interrupts = <0x47 0x8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupt-parent = <0x1>;
interrupts = <0x26 0x8>;
phy_type = "ulpi";
sleep = <0x2 0xc00000>;
};
mdio@24520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {
interrupt-parent = <0x1>;
interrupts = <0x14 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
linux,phandle = <0x4>;
};
ethernet-phy@1 {
interrupt-parent = <0x1>;
interrupts = <0x13 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
linux,phandle = <0x7>;
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x3>;
};
};
mdio@25520 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
linux,phandle = <0x6>;
};
};
ptimer@24e00 {
compatible = "fsl,gianfar-ptp-timer";
reg = <0x24e00 0xb0>;
linux,phandle = <0x5>;
};
ethernet@24000 {
cell-index = <0x0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x3>;
phy-handle = <0x4>;
sleep = <0x2 0xc0000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
ethernet@25000 {
cell-index = <0x1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [00 00 00 00 00 00];
interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
interrupt-parent = <0x1>;
tbi-handle = <0x6>;
phy-handle = <0x7>;
sleep = <0x2 0x30000000>;
fsl,magic-packet;
fsl,lossless-flow-ctrl = <0x0>;
ptimer-handle = <0x5>;
};
serial@4500 {
cell-index = <0x0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0x9 0x8>;
interrupt-parent = <0x1>;
};
serial@4600 {
cell-index = <0x1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0x7f28155>;
interrupts = <0xa 0x8>;
interrupt-parent = <0x1>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <0xb 0x8>;
interrupt-parent = <0x1>;
fsl,num-channels = <0x4>;
fsl,channel-fifo-len = <0x18>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3ab0abf>;
};
sata@18000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <0x1>;
interrupts = <0x2c 0x8>;
interrupt-parent = <0x1>;
};
sata@19000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <0x2>;
interrupts = <0x2d 0x8>;
interrupt-parent = <0x1>;
};
tdm@16000 {
device_type = "tdm";
compatible = "fsl,mpc8315-tdm";
reg = <0x16000 0x200 0x2c000 0x2000>;
clock-frequency = <0x0>;
interrupts = <0x53 0x8 0x5e 0x8 0x3 0x8>;
interrupt-parent = <0x1>;
};
legerity {
device_type = "slic";
compatible = "legerity-slic";
clock-frequency = <0x0>;
interrupts = <0x16 0x8>;
interrupt-parent = <0x1>;
};
gpio@c00 {
device_type = "gpio";
compatible = "fsl,mpc8315-gpio";
reg = <0xc00 0x18>;
interrupt-parent = <0x1>;
};
interrupt-controller@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0x0>;
#interrupt-cells = <0x2>;
reg = <0x700 0x100>;
device_type = "ipic";
linux,phandle = <0x1>;
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0x0 0x100>;
interrupts = <0x43 0x8 0x4 0x8 0x51 0x8 0x52 0x8 0x56 0x8 0x57 0x8 0x58 0x8 0x59 0x8>;
interrupt-parent = <0x1>;
};
power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <0x50 0x8>;
interrupt-parent = <0x1>;
fsl,mpc8313-wakeup-timer = <0x8>;
linux,phandle = <0x2>;
};
timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5a 0x8 0x4e 0x8 0x54 0x8 0x48 0x8>;
interrupt-parent = <0x1>;
linux,phandle = <0x8>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
clock-frequency = <0x7ed6b40>;
interrupts = <0x5b 0x8 0x4f 0x8 0x55 0x8 0x49 0x8>;
interrupt-parent = <0x1>;
};
};
pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <0x7000 0x0 0x0 0x1 0x1 0x12 0x8 0x7000 0x0 0x0 0x2 0x1 0x12 0x8 0x7000 0x0 0x0 0x3 0x1 0x12 0x8 0x7000 0x0 0x0 0x4 0x1 0x12 0x8 0x7800 0x0 0x0 0x1 0x1 0x11 0x8 0x7800 0x0 0x0 0x2 0x1 0x11 0x8 0x7800 0x0 0x0 0x3 0x1 0x11 0x8 0x7800 0x0 0x0 0x4 0x1 0x11 0x8 0x8000 0x0 0x0 0x1 0x1 0x30 0x8 0x8000 0x0 0x0 0x2 0x1 0x11 0x8 0x8000 0x0 0x0 0x3 0x1 0x30 0x8 0x8000 0x0 0x0 0x4 0x1 0x11 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x42 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x1000000 0x0 0x0 0xe0300000 0x0 0x100000>;
clock-frequency = <0x3f940aa>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0008500 0x100 0xe0008300 0x8>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0009000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x1 0x8 0x0 0x0 0x0 0x2 0x1 0x1 0x8 0x0 0x0 0x0 0x3 0x1 0x1 0x8 0x0 0x0 0x0 0x4 0x1 0x1 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x1 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xb1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe0009000 0x1000 0xb0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
pci@e000a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
msi-available-ranges = <0x43 0x4 0x51 0x52 0x56 0x57 0x58 0x59>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x2 0x8 0x0 0x0 0x0 0x2 0x1 0x2 0x8 0x0 0x0 0x0 0x3 0x1 0x2 0x8 0x0 0x0 0x0 0x4 0x1 0x2 0x8>;
interrupt-parent = <0x1>;
interrupts = <0x2 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x10000000 0x1000000 0x0 0x0 0xd1000000 0x0 0x800000>;
clock-frequency = <0x0>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
#address-cells = <0x3>;
reg = <0xe000a000 0x1000 0xd0000000 0x1000000>;
compatible = "fsl,mpc8315-pcie";
device_type = "pci";
};
};

480
Zim/Research/Error_Notes/编译错误/编译新内核(3.1.8)是出现没找到mpc8315erdb-default.dts错误/mpc8315erdb.dts Normal file
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/*
* MPC8315E RDB Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
compatible = "fsl,mpc8315erdb";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8315@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// CS0 and CS1 are swapped when
// booting from nand, but the
// addresses are the same.
ranges = <0x0 0x0 0xfe000000 0x00800000
0x1 0x0 0xe0600000 0x00002000
0x2 0x0 0xf0000000 0x00020000
0x3 0x0 0xfa000000 0x00008000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8315-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x2000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
kernel@100000 {
reg = <0x100000 0x300000>;
};
fs@400000 {
reg = <0x400000 0x1c00000>;
};
};
};
immr@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8315-immr", "simple-bus";
ranges = <0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
mcu_pio: mcu@a {
#gpio-cells = <2>;
compatible = "fsl,mc9s08qg8-mpc8315erdb",
"fsl,mcu-mpc8349emitx";
reg = <0x0a>;
gpio-controller;
};
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
phy_type = "utmi";
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = < &phy0 >;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <20 0x8>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <19 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = < &phy1 >;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <133333333>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <133333333>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3a30abf>;
};
sata@18000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <44 0x8>;
interrupt-parent = <&ipic>;
};
sata@19000 {
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <2>;
interrupts = <45 0x8>;
interrupt-parent = <&ipic>;
};
gtm1: timer@500 {
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
reg = <0x500 0x100>;
interrupts = <90 8 78 8 84 8 72 8>;
interrupt-parent = <&ipic>;
clock-frequency = <133333333>;
};
timer@600 {
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
reg = <0x600 0x100>;
interrupts = <91 8 79 8 85 8 73 8>;
interrupt-parent = <&ipic>;
clock-frequency = <133333333>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: interrupt-controller@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0 0x100>;
interrupts = <0x43 0x8
0x4 0x8
0x51 0x8
0x52 0x8
0x56 0x8
0x57 0x8
0x58 0x8
0x59 0x8>;
interrupt-parent = < &ipic >;
};
pmc: power@b00 {
compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
"fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 8>;
interrupt-parent = <&ipic>;
fsl,mpc8313-wakeup-timer = <&gtm1>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
0x7000 0x0 0x0 0x1 &ipic 18 0x8
0x7000 0x0 0x0 0x2 &ipic 18 0x8
0x7000 0x0 0x0 0x3 &ipic 18 0x8
0x7000 0x0 0x0 0x4 &ipic 18 0x8
/* IDSEL 0x0F -mini PCI */
0x7800 0x0 0x0 0x1 &ipic 17 0x8
0x7800 0x0 0x0 0x2 &ipic 17 0x8
0x7800 0x0 0x0 0x3 &ipic 17 0x8
0x7800 0x0 0x0 0x4 &ipic 17 0x8
/* IDSEL 0x10 - PCI slot */
0x8000 0x0 0x0 0x1 &ipic 48 0x8
0x8000 0x0 0x0 0x2 &ipic 17 0x8
0x8000 0x0 0x0 0x3 &ipic 48 0x8
0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci1: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 1 8
0 0 0 2 &ipic 1 8
0 0 0 3 &ipic 1 8
0 0 0 4 &ipic 1 8>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xa0000000
0x02000000 0 0xa0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
pci2: pcie@e000a000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
reg = <0xe000a000 0x00001000>;
ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 2 8
0 0 0 2 &ipic 2 8
0 0 0 3 &ipic 2 8
0 0 0 4 &ipic 2 8>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xc0000000
0x02000000 0 0xc0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
leds {
compatible = "gpio-leds";
pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "ide-disk";
};
};
};